Shareholders of II-VI and Finisar have voted to approve proposals related to II-VI's acquisition of Finisar. Both companies received enthusiastic shareholder support for the proposals related to the merger agreement first announced on November 9, 2018.

97 percent of the shares of II-VI common stock voting at II-VI's special meeting voted to approve the proposal to issue shares of II-VI common stock pursuant to the merger agreement, and 99 percent of the shares of Finisar common stock voting at Finisar's special meeting voted to approve the proposal to adopt the merger agreement.

The combination of the two companies would form a formidable photonics and compound semiconductor company capable of serving the broad set of fast growing markets of communications, consumer electronics, military, industrial processing lasers, automotive semiconductor equipment and life sciences. Together, II-VI and Finisar employ over 24,000 associates in 70 locations worldwide upon closing of the transaction.

“Since the merger announcement, our shareholders have gained an appreciation of the long-term value creation that the unique breadth and depth of this combination will enable,” said Vincent D. Mattera, Jr president and CEO, II-VI Incorporated. “Meanwhile, the feedback from our major customers in the communications and consumer markets continues to be overwhelmingly positive, due to the high complementarity of our enabling technology, intellectual property, product portfolios and global footprint.”

“While the two companies continue to operate independently, the integration teams are working together to ensure a seamless integration and transition,” said Michael Hurlston, Finisar's CEO. “We see the positive overlap between our cultures, the mutual appreciation for our companies' capabilities, the exceptional synergy potential, and the energizing outlook for our future.”

The merger is expected to be completed in the middle of calendar year 2019. The merger filing is under review in China by the State Administration for Market Regulation (SAMR), in Mexico by the Federal Economic Competition Commission, and in Romania by the Romanian Competition Council.

Raytheon's GaN-based next generation Enterprise Air Surveillance Radar (EASR) - the newest sensor in the US Navy's SPY-6 family of radars - has begun live testing.

EASR has already completed subsystem testing at Raytheon's Near Field Range in Sudbury, Massachusetts. More recently, the 6 foot x 6 foot rotating array was wrapped, loaded onto a flatbed truck and eventually crane-lifted onto a 100 foot test tower at the Surface Combat Systems Centre at Wallops Island, Virginia. Once up and running, the radar will undergo system-level testing, tracking a variety of aircraft through the end of 2019.

The GaN-based Enterprise Air Surveillance Radar, or EASR, is the US Navy's next generation radar for aircraft carriers and amphibious warfare ships, providing simultaneous anti-air and anti-surface warfare, electronic protection and air traffic control capabilities.

"Going from 'cold steel' to a fully calibrated radar in less than one year is no small feat, but that's exactly what we accomplished with EASR," said US Navy Captain Jason Hall, program manager for Above Water Sensors, Program Executive Office Integrated Warfare Systems. "The scalable building block architecture developed for AN/SPY-6(V)1 enabled EASR to rapidly complete subsystem testing. We are making great strides toward delivering SPY-6 capability across the fleet."

Raytheon is building two variants of EASR: a single-face rotating array designated AN/SPY-6(V)2 for amphibious assault ships and Nimitz class carriers, and a three fixed-face array designated AN/SPY-6(V)3 for Ford class aircraft carriers and the future FFG(X) guided missile frigates.

Both versions of EASR are built on scalable Radar Modular Assembly technology as well as a software baseline that has been matured through development and recent test successes of AN/SPY-6(V)1 the US Navy's program of record for the DDG 51 Flight III destroyers. Each RMA is a self-contained radar in a 2 foot square box. These individual radars can integrate together to form arrays of various sizes to address any mission on any ship. EASR also adds air traffic control and weather capabilities to the mature SPY-6 software baseline.

Upon completion of system-level testing in Q4 2019, EASR will shift from the engineering and manufacturing development phase to the production phase. The 1st delivery of AN/SPY-6(V)2 to LHA-8, the America Class Amphibious Assault Ship, is on plan for 2021.

GaN Systems, has announced a strategic partnership with Aveox, a provider of mission critical electro-mechanical power solutions, to significantly reduce the size and weight of the company's 3-phase AC power converters with Active Power Factor Correction (APFC).

This partnership enables the development of power-dense, Aerospace-Compliant power conversion modules for a wide variety of cockpit, galley and cabin equipment that use 3 Phase power.

Aveox's high-efficiency power conversion modules for aerospace and defence systems are designed to replace legacy Transformer Rectifier Units (TRUs) around the world. GaN Systems says its power devices allow the modules to be more than five times smaller than conventional units using silicon technology.

GaN switches have very low losses which enable an efficiency of >97 percent, significantly reducing the amount of heat generated. Using compact GaNpx bottom-cooled devices, Aveox was able to combine both the semiconductor switches and surface-mounted magnetics onto a single Insulated Metal Substrate (IMS) board, making the converter smaller than before possible.

"Running GaN Systems devices at high frequency has enabled us to significantly reduce the size and weight of our newest generation power conversion modules, said David Palombo, CEO of Aveox Inc. Together with GaN Systems, we are excited to see our advanced technologies enable leading aerospace companies to develop some of the world's most efficient and lightest weight power systems for safety critical applications."

"We are excited to be working with leading companies like Aveox and seeing the growing number of innovative, state-of-the-art GaN-based products released in the market, especially in industries where durability and reliability count," said Jim Witham, CEO of GaN Systems."With this partnership, we are seeing how GaN Systems is playing a pivotal role in providing an innovative energy-efficient solution. Most noticeably, there is a significant amount of momentum in various markets, as more companies realise the outcomes with GaN to enable smaller, lower cost, energy-efficient power systems."

VisIC Technologies, a GaN power semiconductor device company, has announced the availability of its On-Board-Charger (OBC) reference design for the fast-growing Electrical Vehicle (EV) market.

The 6.7kW OBC features a size and weight of only 2.3L and 4.5kg respectively, providing close to 3kW/L power density and proving the disruptive capability of GaN switches. This is 3 x better power density compared to commercially available products today. With the efficiency above 96 percent across a wide load range, it helps automotive manufacturers to reduce power losses and enables faster charging for electric car owners.

The 6.7kW OBC using VisIC GaN power devices targets plug-in hybrid vehicles/electric vehicles (PHEV/EV) applications. With a universal 110‐220V/16-32A AC input and 200‐430V DC output for charging the automotive battery by controlling voltage and current flow to the battery. The charger is designed to provide the interfaces to charging standards on the input power side and thus adapts to charging infrastructure.

The OBC design which uses VisIC's GaN technology, designed for Automotive qualification requirements AEC-Q101, demonstrates reduction in power losses, size and weight. The overall advantages include simplifying the cooling systems, reducing the charging time and reducing the size and cost of the EV.

"We are happy to release this OBC reference-design to help our customers to accelerate the design cycle and bring the best-in-class xEV chargers using VisIC's GaN technology to the market in a fast and efficient way," says Ran Soffer, VisIC's SVP sales and marketing. "This reference design proves the benefits and improvements VisIC's GaN technology can bring to the xEV users. With VisIC's GaN technology, electrical cars will be more efficient, lighter in weight and more affordable."

Semiconductor equipment manufacturer ClassOne Technology has sold its Solstice S4 system to Philips Photonics, one of the industry's leading providers of VCSEL devices. The announcement was made by Byron Exarcos, ClassOne Group CEO, and Hans Peter Ehweiner, general manager at Philips Photonics. The new ClassOne equipment will be installed at the Philips facility in Ulm, Germany.

“We will be using the new Solstice S4 for wafer cleaning applications,” said Ehweiner. “So, its unique processing flexibility and high performance are especially useful to us, as well as its small footprint. ClassOne's responsiveness and support for us in Germany are also significant factors in this purchase decision, thus we are looking forward to a fruitful and longstanding relationship."

"Solstice initially built its reputation on quality electroplating," said Exarcos. "But with its Plating-Plus capabilities, Solstice is now recognised as a powerful multiprocessing tool that can handle everything from plating to wafer cleaning, high-pressure metal lift-off, resist strip, UBM etch and more. Phillips Photonics is a perfect example of next-generation fabs that are using Solstice primarily for those additional wet processes. It's also notable that Solstice is becoming the tool of choice for VCSEL manufacturers around the world.”

The Solstice family of wet-processing tools includes the four-chamber Solstice S4 and the eight-chamber Solstice S8, for 75wph, automated wet-processing production, as well as the 2-chamber Solstice LT for semi-automated process development. The platform was specifically designed for ≤200mm wafers, which are used in compound semiconductor and many emerging technologies. With its special Plating-Plus multi-processing capability, Solstice is able to reduce the number of different tools that many users need to purchase. Solstice equipment is also known for being priced significantly lower than similarly configured systems from the large manufacturers. It has been described as providing “Advanced Wet Processing for the Rest of Us.”

With 20 years of history in VCSEL technology, Philips Photonics produces VCSEL-based solutions for data communications, consumer and industrial applications — for security, surveillance, night vision and a range of sensing applications. The company has enabled the introduction of laser-based PC mice, high bit-rate active optical cables, and has introduced VCSEL-based Laser Doppler Technology to consumer applications.

Rohm has announced the addition of ten new automotive SiC MOSFETs. The company says that the introduction of the SCT3xxxxxHR series means it now offers the industry's largest lineup of AEC-Q101 qualified SiC MOSFETs that provide the high reliability necessary for automotive on-board chargers and DC/DC converters.

In recent years an increasing number of automotive makers are offering electric vehicles in response to growing environmental awareness and rising fuel costs. However, although EVs are becoming more widespread, their relatively short driving range remains problematic. To improve driving distance, batteries are trending towards larger battery capacities with shorter charging times. This, in turn, demands high power and efficiency on board chargers such as 11kW and 22kW, leading to increased adoption of SiC MOSFETs. In addition, higher voltage batteries (800V) require power devices featuring low loss and higher withstand voltages.

To meet these needs, Rohm added ten new models to its lineup of AEC-Q101 qualified MOSFETs that uses a trench gate structure. The result is the industry's largest portfolio, available in both 650V and 1200V variants. And going forward, Rohm will strive to further improve quality and strengthen its lineup to increase device performance, reduce power consumption, and achieve smaller size.

In December 2010 Rohm was the first in the world to succeed in mass producing SiC MOSFETs. Rohm established automotive-grade quality and began supplying SiC Schottky barrier diodes for on board chargers in 2012 and SiC MOSFETs for DC/DC converters and on-board chargers from 2017.

Plessey has developed its proprietary 2D planar GaN-on-Si process to emit Green light without the need for colour conversion techniques.

To produce Green light, LED manufacturers typically apply phosphors or quantum dot conversion materials to native Blue LEDs. These materials then convert short wavelength, typically 450nm, Blue light to Red or Green wavelengths with typically 10 percent to 30 percent efficiency.

Plessey's native Green LEDs are formed inherently using its proprietary GaN-on-Si epitaxial growth process similar to the native Blue LEDs with the principal difference coming in the amount of indium that is incorporated in the quantum well structures of the LED.

With no colour conversion losses, the native Green emission is orders of magnitude times brighter than colour converted process for microLEDs. With a dominant Green wavelength of 530nm and a full width half maximum wavelength of 31nm the Green is well suited for colour displays. Additionally, the Green emission exhibits outstanding wavelength stability versus current density.

“Plessey already provides powerful, efficient native Blue microLEDs and through this innovation in our growth technology, Plessey has produced world leading high performance native green micro LEDs which will provide for next generation display and illuminator devices for our customers.” said Mike Snaith, chief operating Officer at Plessey.

Veeco has announced that Aledia, a Grenoble-based developer and manufacturer of next-generation 3D LEDs for display applications, has expanded its portfolio of Veeco thin film process equipment to support the development and production of advanced 3D micro-LEDs.

Aledia cited Veeco's proven leadership in compound semiconductor applications, GaN-on-silicon growth performance, and capability to grow a full range of high-quality epitaxial films as key factors influencing its decision.

“We have been impressed with the performance of Veeco's Propel GaN MOCVD platform for large-wafer 3D LED production, and naturally turned to Veeco again to support our advanced LED development,” said Philippe Gilet, co-founder and CTO of Aledia. “Veeco's solutions meet our rigorous material quality and system delivery requirements along with unmatched material flux stability and repeatability. We are excited to take the next step with them in producing next-generation 3D micro-LEDs.”

The collaboration between Aledia and Veeco reflects the immense promise of micro-LEDs and other advanced LEDs for the future of displays. Micro-LEDs offer high efficiency, brightness and reliability benefits with shorter response time, enabling lighter, thinner and flexible displays with energy saving advantages for applications such as wearables, smartphones, automotive, signage/large TVs, augmented reality/virtual reality, etc. According to a recent Yole Développement report, there have been close to 1,500 patents filed related to micro-LED display from 125 different companies, with the bulk of activity occurring after 2012.

“With the significant shift toward exploration of micro-LEDs for use in next-generation displays, leaders like Aledia are turning to Veeco,” said Gerry Blumenstock, senior vice president and general manager of Veeco's compound semiconductor business unit. “Veeco's proven materials engineering expertise puts us in a unique position to offer innovative thin film deposition technologies for customers tackling tough compound semiconductor research, development and production challenges.”

Just last month, Cree revealed it is selling its underperforming Lighting Products business unit to Ideal Industries. The divestiture follows efforts – spearheaded by chief executive Gregg Lowe - to expand production at Wolfspeed and looks set to drive growth across the coming years.

“This gives us the cash to invest in Wolfspeed and establishes us as a pure-play compound semiconductor company focusing on SiC and GaN,” Lowe tells Compound Semiconductor.

“The cash will help to fund capacity expansions, including our manufacturing footprint and also our research and development resources.”

“Lighting Products was a completely different channel to market and added complexity to our business,” he adds. “But when you have the entire management team and board-of-directors focused on being a pure-play compound semiconductor business, this really allows you to double down and re-invest.”

Indeed, since joining Cree in September 2017, Lowe has single-mindedly worked on bolstering Wolfspeed, having grown the business by more than 100 percent.

Key moves include the acquisition of Infineon’s RF business and also several long-term SiC supply deals worth more than $500 million, including agreements with ST Microelectronics and Infineon.

“We set out to quadruple Wolfspeed revenues to $850 million by 2022 and now this [sale] really helps with that,” highlights Lowe. “We have a faster growth profile, higher margins and a cash balance approaching $1 billion.”

What’s more, Lowe is adamant that the power and RF focus comes at just the right time. As he points out, thanks to the rapid rollout of 4G and 5G networks, the demand for Cree’s GaN-on-SiC RF products is rising.

“This turned on quite quickly over the last two quarters so we’re trying to expand capacity very quickly here,” he says. “Of course our Infineon business acquisition here helped us to get a good foot in that market.”

And at the same time, car manufacturer investments in electric vehicles are increasingly gathering momentum. “Since I joined Cree, around $300 billion of investments have been announced and this is really driving the demand for silicon carbide.”

So what happens now? Lowe is certain that the Lighting Products divestiture works for every party involved. Ideal Industries gains a ‘good platform’ to expand its presence in Lighting and Industrial applications. And as he adds: “It’s a win for employees in the Lighting business as this will now be the largest division in Ideal and the main focus of this company.”

But clearly for the chief executive, Wolfspeed is the priority. Indeed, in past months Cree has been shifting research and development, crystal growth equipment and capital expenditure from its lighting arm to Wolfspeed, more than doubling capacity along the way.

As Lowe emphasises, cash influx from the latest sale will further grow manufacturing capacity, but Cree continues to talk with potential new SiC suppliers. Given this, more supply deals akin to those of ST Microelectronics and Infineon could well follow.

Meanwhile, in a similar vein to his Infineon RF and power business deal, the chief executive isn’t adverse to future mergers and acquisition. Describing these as ‘part of Cree’s ‘toolkit’, he says: “Whatever we do, we will be focused on growing the Wolfspeed business, and if there is a good merger and acquisition opportunity... well we have used that before.”

Importantly, Lowe also intends to plough more cash into research and development, to develop baseline technologies including SiC crystal growth, wafer fabrication and epitaxy capacities, which as he says will further increase yields and drive down costs.

“We will also cover device developments, applications engineering and field application resources as customers start to transition from silicon to silicon carbide power devices,” he says. “There are some application differences we will need to help customers work through and now we can fund these as well.”

And looking to the future, Lowe believes that higher-voltage devices will provide ‘interesting application opportunities’. As he highlights, Cree has demonstrated 20 kV devices, but believes that 650 V devices and those rated a little higher than that will continue to hold the company’s attention.

“The 650 V to 2000 V range is probably the vast majority of the market that we will be going after,” he says. “We want to convert the industry from silicon to silicon carbide and this means expanding our product portfolio, expanding customer reach and enabling new markets to make this transition.”

Be it for photovoltaics, electric vehicles, 5G infrastructure or industrial high-power supplies, SiC is steadily infiltrating markets around the globe. As analysts forecast a compound annual growth rate of at least 25 percent, and a $1.5 billion SiC market come 2023, industry players up and down the supply chain are readying for action.

US-based GT Advanced Technologies recently opened a SiC crystal growth facility to meet the imminent SiC market boom while Infineon has bought SiC wafer-splitting process developer, Silectra, to secure substrate supply.

Wolfspeed, Infineon, GeneSiC and more are diligently pioneering packaging structures to take on the extreme switching speeds and temperatures that SiC can handle. And in a bold move, Cree has sold its Lighting business to focus on power semiconductors, having spent the last year-and-a-half year bolstering its SiC supply and honing devices.

Amongst these front-runners is Japan-based Rohm, having had its eyes firmly fixed on SiC for some two decades. Preliminary SiC MOSFET development began in 2002, with initial samples shipped in 2005. Trial manufacture of 300A MOSFETs followed in 2007 with trench-type devices released in 2008.

Then, in 2009, the company acquired SiC crystal manufacturer, SiCrystal, with the now vertically integrated business delivering its first mass-produced SiC Schottky diodes and MOSFETs in 2010. Mass-produced full SiC modules followed in 2012 with Schottky barrier diodes on 6-inch wafers delivered in 2017.

Today, the company claims to have the industry’s largest line-up of automotive-grade 650 V and 1200 V SiC MOSFETs, but is also intent on delivering devices at ever-higher voltages for more and more gruelling applications. As Aly Mashaly, Power Systems Manager at Rohm highlights, the industry trend towards higher power density has led to higher systems voltages. And, given this, the company recently developed a 1700 V, 250 A rated SiC power module that is currently being used in customer projects.

According to Mashaly, the module’s high voltage surpasses the requirements of electric hybrid vehicles, for now, but is instrumental in inverted and converter applications for outdoor power-generation systems and industrial high-power supplies.

Crucially, the latest system promises to provide the same energy-saving performance as 1200 V devices with a high reliability, meaning the 1700 V SiC module is ready to take on the 1700 V silicon IGBT module.

“The big challenge in silicon carbide is to provide high reliability, especially at higher voltages,” says Mashaly. “But we have tested our devices at high voltages, temperatures up to 85 °C and high humidities, and for more than 1000 hours, and we haven’t seen any degradation in performance.”

The module comprises SiC MOSFETs and Schottky barrier diodes, vastly diminishing chip area and reducing on-resistance by 10 percent relative to similar SiC products, says Mashaly. But while this cuts energy use and heat dissipation, it doesn’t cut upfront costs, a fact that the Power Systems Manager knows only too well.

“We are working to reduce the level of the price compared to the IGBT [module], and while I cannot provide exact numbers, I do know that we will always be getting closer,” he says. “I don’t ever expect the cost of the SiC module to come down to that of the IGBT module but if we look at system cost , the benefits of using SiC has already been proven to many tier one companies and automotive OEMs.”

So with the demand for SiC power devices rising, how exactly is Rohm meeting market needs? While the company is in the process of ongoing capacity expansion at its Nuremberg site, in June 2018 it revealed plans to massively expand SiC production capacity at its Apollo plant in Chikugo, Japan. Construction has now started and will continue until at least the end of 2020.

At the same time, the transfer of manufacturing from 4-inch to 6-inch wafers is also well underway, boosting production efficiencies. “We have already started this for our planar MOSFETs and this year we will try to make this transition with our trench MOSFETs,” says Mashaly.

What’s more, Mashaly reckons that the wafer quality of Rohm’s 6-inch wafers is better than that of its 4-inch wafers. “We have nineteen years of experience in SiC and we saw a huge improvement in the quality of [our] four-inch wafers compared to two-inch wafers, and we now see that quality is even better with the six-inch wafers,” he says. “Year by year we have this improvement in our production process and we are confident that the quality in the next level of substrate will be high.”

So with manufacturing in hand, where next for Rohm on the road to SiC success in an increasingly crowded market-place? Mashaly is keen to highlight that aside from Wolfspeed, Rohm is the only vertically integrated business in this market, and as such, intends to capture 30 percent market-share by 2025, making it the number one player.

And as well as an ever-larger market share, the company will also be looking towards ever-higher voltages. “Right now we are focusing on the 1200 V and 1700 V areas due to the big potential for mass production of SiC here,” he says. “But we already have research and development activities in place for 3.3 and 6.5 kV [devices]... we don’t have a defined time when we will launch these products but we also see the potential for SiC here.”

We are in the midst of the Fourth Industrial Revolution. Innovation in manufacturing is underway, thanks to integration of conventional production and network connectivity with the Internet of Things (IoT) and Artificial Intelligence (AI). The benefit of this is that it enables AI manufacturing – that is, the use of production processes that are managed through intelligent machines, systems, and networks that autonomously sense and analyse information.

The adoption of AI and IoT is already driving big changes within a range of industries. Armed with AI, manufacturing processes can be monitored in real-time through the sensing, collecting, and analysing of sensor data using IoT. This capability allows the swift identification and resolution of problems in manufacturing facilities, leading to enhanced productivity. Ultimately, it will enable many tasks to be transferred from human engineers to AI systems, and create a seamless manufacturing environment.

At IVWorks, a GaN epiwafer foundry start-up headquartered in Daejeon, South Korea, we are moving with the times. We have developed and applied a deep learning-based AI epitaxy platform, known as Domm, that dramatically improves the productivity and scalability of MBE-grown epiwafers. This patented technology, which uses a deep learning algorithm to detect and analysis electron diffraction patterns, monitors crystal growth at the atomic level in real time.

Today, we are using our Domm platform on three MBE systems that produce 100 mm to 200 mm GaN epiwafers for DC and RF power devices. We monitor the electron diffraction pattern with a deep learning algorithm, and information about the entire crystal structure of the epiwafer is classified and converted into data. If abnormal patterns are identified, an alarm is raised with the engineer. This level of adoption of AI is referred to as Level 2 (see Figure 1 for an overview of the different levels).

This is just the start of our venture into AI. In February 2019, we closed a $6.1 million series B funding round that will enable us to expand our manufacturing capabilities and upgrade the Domm platform to higher levels (see Figure 2 for our roadmap). The first step will be a move to Level 3, the AI Assistance level. Here, data acquired through the deep learning algorithm is learned by correlating it with the quality data of the produced epiwafers. This allows the probability of pass/fail to be intelligently predicted in real time, assisting the engineer.

Further ahead, we will move to Level 4 and then on to Level 5. The lower of these is known as the AI Production level. This bolsters yield by automatically revising the process conditions of the recipe in real time, according to the predicted probability of pass/fail. When operating at Level 5, known as the AI Manufacturing level, it is possible for AI to develop a customized epiwafer recipe of a new structure. To accomplish this, epiwafer quality results, according to recipes, are accumulated and learned. In addition, correlations are established, and their validity analysed.

The need for AI

The use of AI makes a dramatic impact on MBE, due to the complexity of this growth process. Successful growth of epiwafers demands strict control of many conditions, including: the substrate temperature; the temperature distribution of the substrate and the reactor; the internal pressure inside the reactor; the number of source atoms; the relative ratio between the sources; the growth rate; the size and geometry of the reactor; the flow pattern and the flux pattern of the source; and atomic migration (or diffusion), which includes binding reactions on a substrate surface. To illustrate this complexity, just consider the growth of a 3 µm-thick GaN FET epiwafer. It is formed by depositing approximately 12,000 or more atomic layers, each added with precisely controlled conditions (see Figure 3).

So complex is the growth process that two nominally identical models of the same state-of-the-art MBE reactor have different optimum conditions. And maintaining the conditions in either of them is far from easy – it takes an engineer with significant expertise to secure and maintain reproducibility that satisfies pass/fail tolerance for target characteristics, even when the same recipe is being used on the same reactor, run after run after run.

The conventional approach to managing productivity is for an engineer to collect and analyse data related to the epitaxial growth process conditions, the equipment status, and the results associated with the quality of the manufactured epiwafers. However, comprehensive analysis of the epi-structure and the process are challenging, and this can lead to variations in the analysis of the collected data, depending on the expertise of the engineer. When the collected data is difficult to quantify, variations are exacerbated, compromising the reliability of the results of the analysis, and ultimately hampering efforts to control and monitor the epiwafer manufacturing process. Since limits on human resources often cause bottlenecks in productivity and scalability, there is a great demand for a highly advanced, automated solution that is efficient, convenient, and capable of a real-time, seamless response that maximises the manufacturing productivity of the epiwafers.

Gaining the edge with AI

To develop automated solutions that maximise epiwafer manufacturing productivity, it is critical to employ quantitative monitoring of both the process state of the equipment and the growth state of the epi-structure. Given that the focus has to be on maximising the yield of products and managing the manufacturing process to ensure that the material is as close as it can be to the target characteristics, process conditions should be ideally corrected in real-time during epitaxial growth. And if that’s not possible, the recipe must be updated after every growth.

Automation of the monitoring process requires the collection of monitoring data that has high validity and a high degree of correlation. Options for monitoring epitaxial growth in today’s commercial reactors include thermocouples, infrared temperature sensors, pressure gauges, residual gas analysers, optical-based flux monitoring tools, and gas flow monitors. If insight is required into either the growth state of the epi-structure, the growth rate or the wafer curvature, measurements and monitoring can be provided with reflectometer and deflectometer methods.

However, note that for the manufacturing of epiwafers, with the techniques just listed, quantitative automated monitoring is yet to be applied that identifies the crystal growth modes and the crystal structure formation at the atomic level. This knowledge is important, as it can determine the characteristics of epiwafers. Fortunately, it can be determined during MBE growth, which takes place under vacuum, using reflection high-energy electron diffraction (RHEED). This form of electron diffraction can reveal crystal quality, crystal composition, crystal growth rate, and V/III flux ratios in real time with atomic layer resolution. To do this, an electron beam is directed onto the surface of a substrate under crystal growth, and the reflected electron diffraction pattern is analysed.

One of the great strengths of RHEED is that it offers real-time, direct measurements of the crystal growth state that are highly correlated with the quality of the epiwafers. However, as the measured data is in the form of an image of the diffraction pattern (see Figure 4), its interpretation requires an engineer with expertise. Even then, the engineer can only undertake simple numerical analysis or empirical analysis to gain an insight into the crystal growth. It is difficult to quickly interpret various diffraction patterns, so when an engineer uses the technique, it is confined to R&D, and not applied to production. That’s partly because a large amount of data is obtained on each atomic layer, and as there are thousands to tens of thousands of them in an epiwafer, an overwhelming amount of data is created.

The good news is that these limitations can be overcome with AI image analysis technology and big data technology. In fact, this pairing is so powerful that it is highly likely to exceed the interpretation ability of any human engineer.

Historically, AI image analysis has been a two-step process. Initially, engineers extract the main features of the objects for modelling and design, before AI and big data takes over, detecting and analysing objects. For example, for a cat in an image, engineers pick out features, including two pointed ears, as well as the arrangement of the nose tip, the forehead, and the chin within certain angles on a round face. They then sophisticatedly model and input this type of information for detection and analysis.

Figure 4. Real-time monitoring of the surface atomic structure during the epitaxial growth.

Recently, however, AI has moved on. Now a machine can distinguish objects in images by training, using just data itself, rather than requiring preliminary work from an engineer. The machines of today can distinguish objects in a new image by learning validity and correlation of the images on the database – they don’t need information on the actual object (see Figure 5).

This AI algorithm, called ‘deep learning’, is a major breakthrough for classifying and interpreting RHEED measurements. It allow systems to monitor, in real time, the crystal characteristics for every atomic layer in entire epistructures.

With RHEED patterns, the surface crystal structure of an epiwafer is captured by the shape of an electron diffraction pattern. For example, streaky patterns represent two-dimensional growth, those that are spotty signify three-dimensional growth, and rings reveal polycrystalline growth. Within all these patterns, there are details of crystal structure characteristics, captured in the degree, spacing, and brightness of each pattern (Figure 6).   

When deep learning is used to recognise RHEED patterns, an inference model is created that automatically extracts high-level abstract knowledge and classifies the pattern. Features within the pattern are subjected to a multi-step feature extraction process, using the deep neural network. Quantitative modelling of RHEED patterns is difficult, because the electron diffraction patterns display various crystal growth states. However, this technology is able to automatically detect and classify various electron diffraction patterns, using inference-model, automatically learned features from the input data (see Figure 7). What’s encouraging is that the performance improves proportionally with the amount of training data, and promises to exceed that of an engineer.

Using our Domm platform we can create a prediction model. It is formed by learning the validity and correlation of the dataset that integrates the classified RHEED patterns, growth conditions, and the quality results of the epiwafers. We can apply this prediction model to epiwafer manufacturing to maximise productivity (see Figure 8). 

During the production of GaN-on-silicon FET epiwafers with a basic structure, our Domm system collects RHEED pattern images at up to 30 frames per second, from the beginning to the end of epiwafer growth. Commencing with thermal deoxidation on the silicon surface, and on to the growth of the AlN seed layer, the GaN buffer layer, the AlGaN barrier, and SiN passivation, our system detects and classifies the shape of the diffraction pattern for each atomic layer, along with the transition of patterns. Our model is capable of accomplishing this, thanks to training through deep learning for the entire structure. As a result, Domm monitors and intelligently analyses the manufacturing process, in addition to collecting data on growth conditions and equipment status, and determining pass/fail results.

It is challenging to determine the crystal structures of the GaN buffer layer and the GaN/AlGaN heterojunction interface. However, we are able to gain insight into this by monitoring the setting conditions – including substrate temperature, shutter sequence, and source cell temperature – and the patterns produced by the surface of the wafers, the deoxidation process, and the seed layer. What’s more, by quantitatively measuring pattern transition during the formation of the interfaces surrounding each layer, we are able to quantify the level of similarity with the manufacturing of pass products. When these results are used to predict yield in real time, or sub-standard quality, this can boost productivity, either by requesting a correction to the engineer or by automatically correcting the recipe (see Figure 9).

Our efforts could help to ignite the use of AI within the compound semiconductor industry. Right now, AI is attracting more attention in the likes of: radiology, for medical diagnosis; autonomous driving for automobiles; robotics; and new drug development.

As compound semiconductor manufacturing involves a number of different, complex processes that are conducted step-by-step, this hampers the construction of effective, high-quality input datasets needed for AI. But this could start to change, now that we are demonstrating that RHEED patterns can offer high-quality input data that ultimately provides the highest level of resolution for semiconductor crystal structures. 

However, we are in an envious position, since epiwafer production is a single-process manufacturing field. For us, the crystal growth itself becomes the product, making it a potentially optimal field for the application of AI manufacturing technology.

Figure 9. RHEED pattern detection and classification by Domm platform.

A great way to strengthen the case for a new technology is to highlight how much better it is than the incumbent. That’s the strategy that has been pursued by the pioneers of wide bandgap power devices. For many years, they have been demonstrating the significant energy savings resulting from more efficient power conversion, and the beneficial implications, including a trimming of electricity bills and an increase in the deliverable output from solar panels.

Right now, however, this industry has a new, even better story to tell –and one that is sure to capture the public imagination. It stars an underdog in the form of Venturi, a racing team that has a far smaller budget than many of its rivals. Off the pace for several seasons, it has been improving of late, and this March it caused an upset by netting its first win in the Formula Electric class. What’s is the secret to this success? The adoption of a new, superior technology, in the form of an all-SiC power module produced by Rohm.

Details of this winning module and the benefits that it delivers were discussed by Aly Mashaly, Director of Power Systems at Rohm Semiconductor, during a keynote presentation at this year’s CS International. At this meeting, held in Brussels on 26-27 March, Mashaly revealed that the benefits of using SiC, rather than silicon, were not confined to just delivering greater power from the battery. Instead, they extend to a 30 percent decrease in the size of the unit, as well as a reduction in its weight, which fell from 15 kg to just 9 kg. These improvements, which stem from the opportunity to use smaller passive components, are incredibly valuable – they allow the module to be placed in the ideal spot within the car, leading to better handling. 

Venturi’s foray into SiC power electronics is relatively new. Back in season two (2014-2015), it employed an all-silicon module in its Formula E car. In season three, this evolved to the pairing of a silicon IGBT and a SiC diode, and from season four onwards, it has used the combination of SiC diodes and SiC MOSFETs.

Initially, Venturi’s cars were equipped with a 200kW inverter, operating at a 16kHz switching frequency. Replacing the silicon electronics with SiC enabled an increase in switching frequency to 24kHz, for an inverter producing an output of 220kW. Efficiency at the maximum power increased by more than 1.3 percent, and the maximum efficiency went up by 1.1 percent. However, these figures fail to show the true benefit of the switch to SiC. During racing, cars operate at a variety of loads – and at a partial load, the efficiency with SiC power electronics is more than 5 percent higher than it is with silicon.

The strengths of SiC will benefit not just racing cars, but all electric vehicles. Mashaly explained that for a car with a 33kWhr battery, switching to superior electronics can extend the driving distance – evaluated in terms of a reduction in battery charge from 100 percent to 10 percent – from 159 km to 177 km. Alternatively, a smaller battery can provide the same driving range. Given the high cost of the battery, this can lead to a reduction in total expenditure.

Europe leads the way

Delegates gained further insight into the growing markets for wide bandgap power electronics, along with advances related to device design and production, in many other talks given at CS International. They included an insight into the electric and hybrid electric vehicle market by Hong Lin, Senior Analyst at Yole Développement.

Her analysis, which shows that where the substantial investment in electric and hybrid electric vehicles is coming from, will raise a few eyebrows. While Tesla is grabbing headlines, it is by no means making the biggest investment in this technology. According to Lin, Elon Musk’s firm has invested around $10 billion, while Volkswagen has devoted nearly ten times that to develop this technology. That substantial sum is helping Europe to lead the way, investing $150 billion, compared with $107 billion for Asia and just $39 billion for the US. Lin explained that sales of electric and hybrid electric vehicles will rocket over the next few years. She revealed that they hit 5.8 million last year, are tipped to climb to more than 10 million by 2020, and will exceed 25 million in 2024. Growth will occur in all forms of vehicle – mild hybrids, full hybrids, plug-in hybrids and battery-powered electric vehicles.

There are opportunities for wide bandgap power electronics in the DC-to-DC converters, the main inverter, the generator, and the on-board battery converter. According to Lin, switching from silicon to SiC devices could boost the battery voltage from 400V to 800V, and enable an increase in the driving range.

In mild hybrids, electronics convert the 12V output from the battery to 48V, which is used for the likes of air-conditioning, the brakes, and electric power steering.  This task is a “perfect target for GaN”, argued Lin.

Substrate concerns

A view on where all the markets for SiC and GaN power devices stand today, and what can be expected over the next few years, came from Richard Eden, a Principal Analyst at IHS Markit. Projections provided by him suggest that the global revenue for SiC totalled about $0.5 billion in 2018, will double by 2020, and then climb to almost $5 billion by 2026. In comparison, worldwide sales for GaN power devices will net around $150 million this year, and will rocket to $1.8 billion by 2028.

Two significant markets for SiC devices are photovoltatic inverters – after early success deployment of SiC fell, but it is rising again – and power-factor-correction in power suppliers. But both these sectors will be far smaller than that for electric and hybrid electric vehicles, which will take the lion’s share in the coming years. 

Eden does not expect SiC to make a significant impact in either traction, industrial motor drives or wind turbines. Current handling is the issue in all these applications. “You need hundreds of amps, not tens of amps,” argued Eden.

A major concern within the SiC market is the supply of material. Although many substrate supplies have entered the market, including Dow DuPont, II-VI Advanced Materials, Norstel, Showa Denko and Sumitomo, Eden believes more are needed. Wolfspeed still dominates, with material in such high demand that Infineon Technologies and STMicroelectronics have recently negotiated supply agreements to guarantee substrate supply.

Eden noted that there has been a shift from 4-inch to 6-inch substrates, a move that was hoped to reduce costs by around 50 percent. However, this promise has not been fulfilled, due to a fall in yield.

Device results for SiC are encouraging. There are now trillions of hours of device field experience available, and data suggests that SiC diodes and transistors do not have reliability issues. What’s more, the manufacturers of these devices are meeting JEDEC and automotive AEC-Q101 standards.

Another advance is the expansion of the SiC portfolio. There are launches of SiC MOSFETs and JFETs operating at lower voltages, such as 900 V, 800 V and even 650 V. This shift enables SiC MOSFETs to go head-to-head with silicon super-junction MOSFETs with identical voltage ratings.

Dynamics in the wafer and epiwafer markets for GaN are very different from those in the SiC industry. The majority of GaN power devices are grown on silicon, so substrate supply is not an issue. Those that are making these devices can draw on the services of epiwafer providers, but that’s uncommon, says Eden. Instead, most the of production by IDMs and by foundry services involves in-house epitaxy.

The majority of GaN-on-silicon production is on 6-inch wafers, with volume ramping slowly, while 8-inch GaN-on-silicon is yet to take off. Alternative foundations for GaN are failing to make much headway, according to Eden. Although growth on bulk GaN is being aided by the reduction in the price of the substrates, due to the collapse of the laser diode market, interest in this approach has taken a knock, due to the collapse of Avogy, the premier pioneer of this technology. Meanwhile, other alternatives –  sapphire, SiC and ceramic wafers, such as that made by Qromis –  are known to offer performance benefits, but they are perceived to be unnecessarily expensive compared with GaN-on-silicon.

When it comes to devices, GaN transistors are now in mass production, being deployed in server and telecom power supplies, and also in power adapters and chargers. Automotive systems suppliers are also looking at this technology, which is being considered for on-board chargers and DC-DC converters.

Printing transistors

One option for increasing the capability and commercial impact of GaN power technology is to unite it with silicon CMOS. At X-Fab, they have been developing processes to do just this, which were detailed in a presentation given by project manager Ralf Lerner.

Lerner argued that the benefits of GaN and CMOS integration include: reductions in interconnect distances and losses, leading to improved performance; a smaller form factor; a trimming of power consumption; and lower costs.

According to Lerner, there are two types of approach for this form of integration. One is monolithic. However, when this is performed on CMOS, the challenge is to address the incompatibilities in materials and thermal budgets; and when this is undertaken on GaN, the resulting technology is held back by being restricted to simple logic, and a lack of GaN PMOS. The alternative, heterogenous integration, can be accomplished by either direct wafer bonding, which is impaired by restrictions on chip size and wafer diameter – or by micro-transfer printing, the approach adopted by X-Fab.

Engineers at this fab start with a densely packed source wafer, and use an elastomeric stamp to transfer arrays of dispersed devices to a target wafer. Etching silicon beneath the transistor aids the removal of the devices, with a fast pick-up providing high adhesion, and a slow release producing weak adhesion that assists the printing process. On-wafer metallisation completes heterogeneous integration.

Measurements on transistors with a 17 µm gate-drain spacing, made using devices with an epitaxial thickness of just 5 µm, produce a drain current of just 1 µA at 1800 V. According to Lerner, the breakdown is primarily determined by the lateral gate-to-drain spacing, rather than the buffer thickness.

There are drawback with this printing approach. Yield depends on more factors than it would do for a conventional approach, as it is influenced by the quality of the source wafer, the target wafer, and the printing yield. There is also a trade-off between printing costs and material losses. However, this printing approach also has many merits. Lerner pointed out that: it allows for optimised processes for CMOS and GaN; it offers flexibility in chip and wafer dimensions; and it realises a low ohmic metallisation at the wafer-level, which aids heat spreading. 

Boosting blocking voltages

For blocking voltages of 1 kV or more, the leading rival to silicon is SiC. But GaN can also operate in this domain, thanks to a variety of advances in GaN-on-silicon technology. These include improvements to epitaxial growth and selective removal of silicon. Both options were discussed by Farid Medjdoub in a keynote presentation.

Medjoub began his talk by championing the lateral GaN device, which is the more common architecture.  He argued that its merits include the highest electron mobilities and the best cost-to-performance ratio.

The challenge to realising a higher blocking voltage, such as 1 kV or more, is the need for a thicker buffer layer, which can increase wafer bow and defect density, while compromising reliability.

Carbon-free buffers, produced by drawing on expertise at Allos Semiconductors, address all these issues. For a 6.6 µm-thick buffer featuring several interlayers, GaN-on-silicon epiwafers have a concave bow of just 23 µm, while trapping of carriers in the material is low all the way up to 1 kV. “The vertical breakdown voltage is 1400 V, which is state-of-the-art,” said Medjdoub.

He has also evaluated material from EpiGaN, which has a total thickness of just 5 µm. Using a reference buffer that has been optimised for 650 V applications, measurements on the heterostructure reveal very low trapping up to 1.2 kV. “This is another example that 1200 V is reachable with GaN-on-silicon,” argued Medjdoub.

Even higher voltages are possible with selective substrate removal. Values of 3 kV have been reached by first removing the silicon below the buffer layer, before adding a 15 µm-thick film of AlN by PVD, followed by a 2 µm-thick film of copper. Medjdoub and his co-workers are now working with

ON Semiconductor to apply this approach to industrial devices that are 4 mm-wide, normally-off, and capable of delivering a current of 10 A or more. Testing shows low trapping up to 3 kV, indicating that the silicon replacement does not induce additional trapping effects. 

During the production of power devices, epiwafers are inspected for quality control. It is usual to use bright field, dark field and differential interference contrast to identify and categorise defects on the surface. But what about buried imperfections?

According to Shivanui Lyer, a solutions architect at Nanotronics, these can be exposed by ultra-violet photoluminescence. In her presentation she showed a wide range of defects, exposed by ultra-violet photoluminescence with different excitation wavelengths.

Classifying defects is time-consuming and tricky, and the use of artificial intelligence promises to streamline and improve this process. Nanotronics have taken this approach, investigating the capabilities of artificial intelligence and comparing the results with those obtained with an operator. When they discovered a discrepancy, further investigation revealed human error. “We were thrilled. We had achieved super-human results,” remarked Lyer.

Superior SiC substrates

With demand for SiC substrates at a high, it is important that this industry obtains a high yield from every wafer, to ensure as many high-quality devices as possible get to market.

One way to do this, argued Revasum’s CTO, Robert Rhoades, is to use single-wafer processing, along with robotic handling. He claimed that compared to a batch approach, this enables a higher degree of precision, increased reliability, and ultimately a boost in yield. “Yield is key,” argued Rhoades. “It trumps other concerns.”

Revasum’s single-wafer tools are used to polish substrates. They employ a grinding approach, with a fixed abrasive. This is said to lead to far less sub-surface damage to the substrate than the batch-based lapping approach, which employs loose abrasive and creates more sub-surface damage. Note that the removal of material is far faster with grinding, so the throughput of the multi-wafer tool is not as significant as one might expect.

Another benefit of the single-wafer process is that during the polishing process, the slurry and debris, described by Rhoades as being like “microscopic concrete”, is less likely to adhere to the substrate. This means that with a batch approach, the slurry and debris might dry on the wafer during unloading, a situation that does not occur with single wafers, which benefit from a wet-in, wet-out process.

Getting the best out of every substrate is essential right now. Demand for SiC transistors and diodes is increasing, and must be fulfilled with high-quality products to support further growth in the market. With GaN, it’s a slightly different story.

Here, sales are smaller, but again a great future awaits. To find out just how good it will be, and get an update on the progress of all wide bandgap devices, make sure you attend next year’s CS International.

In the run-up to the turn of the millennium, a silent revolution took place in the silicon power electronics industry. Back then, the on-resistance of commercial transistors plummeted by a factor of between three and ten, thanks to the introduction of a superjunction architecture in unipolar, high-voltage devices. To create this device, a super-junction is formed by creating p-type, high-aspect-ratio columns in n-doped vertical drift zones (see Figure 1).

Today, the super-junction is a cornerstone of the silicon power industry. It features in Infineon’s CoolMOS, ST-Microelectronics MD-Mesh, Fuji’s Super J MOS series, ON Semiconductor’s Super FET and Toshiba’s DTMOS. This class of devices, which is tending to operate in the 500 V to 900 V range, is serving in switched-mode power supplies in phones, laptops, computers and even server farms. They are a invisible, integral part of our daily lives.

One of the attributes of the super-junction transistor, compared with conventional devices, is a higher doping concentration in the n-doped vertical electron conducting path. Blocking capability of the device is maintained by the p-columns, which provide local charge compensation, thereby ensuring that the global electric field is low. Thanks to this,

super-junction transistors provide an ultra-low ohmic switch with a high blocking capability. That’s great from the perspective of a chipmaker, as they can manufacture chips that are smaller – and thus cheaper – for a given on-state resistance. What’s more, these chips can fit into smaller packages.

Recently, sales of silicon power devices have faced ever-stronger competition from those based on SiC. This rival is setting a new benchmark for the efficiency of high-voltage diodes and transistors, which are being deployed in solar panels, wind turbines and electric cars. However, SiC chips are costly, so they need to improve their bang-per-buck. 

Following in silicon’s footsteps

A great way to do this is to bring to market SiC super-junction devices. This would lead to a step-change in on-resistance, and propel energy efficiency to a new high, particularly at the highest blocking voltages of 1.7 kV or more. These attributes would allow products to serve in the likes of solid-state transformers and highly efficient energy-transmission systems in high-speed trains.

Note that a related device, the SiC IGBT, is not up to this task: it suffers from a high threshold voltage – it is typically 2.7 V –  and bipolar degradation of the material is an issue. Although the latter problem can be overcome, the most common solution so far is a very costly selection of the seed material and a significantly thicker epitaxial layer, leading to additional cost.

SiC super-junction devices also promise to lower the price of this wide bandgap technology, as chips can be smaller, and thus cheaper. Note that as the nominal breakdown voltage rises, the difference in drift-layer on-resistance between the super-junction design and that of the conventional, unipolar device grows, offering the potential for a greater reduction in chip size (see Figure 2). 

Arguably, the biggest challenge associated with the commercialisation of the SiC MOSFET is the development of suitable, high-volume processes for the manufacture of these transistors. It is not possible to simply adopt the techniques used for making silicon superjunction MOSFETs, due to significant differences between the two materials.

For silicon super-junction devices, manufacture tends to involve a multi-epitaxial approach. It begins by ion implanting p- and n- areas side-by-side in an undoped epitaxial layer to define the p-type pillars. Another epi layer is deposited on top, before the implanting process is repeated. Carrying out these steps up to five-to-ten times creates ohmic p- and n-pillars, which are then subjected to a high-temperature diffusion process (see Figure 3).

With SiC, this approach is not an option. That’s because conventional dopants, such as aluminium and nitrogen, have extremely low diffusion coefficients. This means that it is infeasible to diffuse over distances of 3-5 µm, which are required in SiC super-junction designs.

Whatever approach is used has to ensure charge-balancing in the device – and so must realise highly precise doping. That rules out technologies like p-doped epi trench filling, because the doping accuracy in the high-volume production of SiC epitaxial layers is rarely better than between +/- 10 percent and +/-20 percent.

The good news is that there is a solution that is applicable to high-volume production: ion implantation, but without diffusion. We are pioneering a form of this at mi2-factory in Jena, Germany. Our technology is capable of producing deep custom-tailored dopant profiles, and while its application to semiconductor manufacturing is new, in a slightly modified flavour it has been successfully applied in heavy-ion cancer therapy for many years.

Our approach differs from the conventional one, whereby monoenergetic ions are ‘shot’ into a pre-defined depth region known as the projected range. In that case, for a given substrate and ion combination, the projected range is just defined by the ion energy. A single shot creates a gaussian peak of implanted ions. However, it is possible to form extended profiles by creating a sequence of many gaussian profiles, each originating from a different implant energy (see Figure 4).

Unfortunately, extended profiles require many shots. Simulations suggest that an extended depth range of a few micrometres requires a sequence between 25 and 50 individual implants with differing energies. That’s expensive, complicated and error-prone.

We advocate a far simpler approach: one shot, one ion energy and a very special filter. Known as energy filter for ion implantation, our technique involves the use of a micropatterned membrane, which converts a monoenergetic ion beam into a continuum of ion implant energies (see Figure 5). With the membrane in the path, ions are ‘shot’ not only into one depth, but simultaneously into all depths, where maximum depth is defined by the primary ion energy. With this approach, continuous depth profiles are accomplished in a very straight forward manner (see Figure 6).

Armed with our technology, high-volume manufacture of SiC super-junction transistors is possible. Our approach eliminates the need for diffusion, replacing this with a technique that delivers an extremely high level of precision. Production costs are low – just one step is required for ion implanting, with a process that is capable of both aluminium p-type doping and nitrogen n-type doping.

One of the primary limitations of our approach is the limited availability of mega-electron ion beams for SiC wafer manufacturing. To address this we offer SiC chip manufacturing customers a loop process option. This serves those in pilot production, and those manufacturing quantities up to medium-volume production – that is, several hundred wafers per month. For higher volumes, we recommend that fabs install industrial tandetron implanters. Further down the line, we plan to refine our technology so that it is compatible with much simpler ion-implantation equipment, rather than just today’s industrially applied electrostatic tandetrons.

Although the membranes for our energy filter for ion-implantation technology are consumables, that does not prevent them from supporting stable, reliable processing. Depending on the ion dose, as many as one hundred  6-inch wafers may be implanted with just a single membrane. Given the very low membrane cost per implant, chip costs generally fall when using our technology, due to benefits that include a reduction in device dimensions associated with the super-junction design.

While our ion-implantation technique may make its case most strongly for the super-junction transistor, it also has a role to play in improving the performance of other SiC power devices, via improvements in doping accuracy (see Figure 7).  

For example, 600 V and 1200 V SiC diodes can benefit from our technology. In these devices, the drop in forward voltage is primarily determined by drift layer doping level and thickness – and optimising these two characteristics is governed by the available epi processing technology. For instance, to head off the impact of unintentional low doping levels that result from process variations, SiC diodes are generally designed larger than they would be if optimum processing conditions were available. By switching from in-situ doping during epi deposition to our superior energy filter for ion-implantation technology, we estimate that it may be possible to shrink the area of the 1200 V device by about 20 percent.

This claim for a reduced chip size is supported by work that we carried out several years ago. Back in 2014, in collaboration with an industry partner, we took part in an R&D project to investigate the impact of doping precision. During this programme, we compared the variations in key characteristics of 600 V merged p-i-n Schottky diodes from regular production with those formed with our ion-implantation technology. We found far narrower parameter distributions for differential resistance, blocking voltage and leakage current, highlighting the potential of our energy filter for ion-implantation technology to reduce chip sizes (see Figure 8). 

Figure 7.  The energy filter for ion-implantation technology developed by mi2 factory can be used for making diodes and transistors.

Today, our technology is well-placed to provide the essentially homogenous doping profiles that are needed for diodes and super-junctions. In future, the design of these devices is tipped to evolve, with the introduction of graded drift-layer doping profiles that will propel efficiency to a new level. We intend to support this, having just started to develop an advanced form of our technology that will be capable of delivering more complex doping profiles.

To support this work, and ultimately our customers, we have developed a software tool that is capable of simulating all types of filter-substrate constellation. This includes masked substrates (see Figure 9).

We are confident that interest in our technology will grow. The SiC super-junction is destined to deliver a hike in power-transistor efficiency, and our energy filter for ion-implantation technology is a key enabling technology for the production of these devices. Other diodes and transistors will also benefit from our approach to doping, with the greater accuracy provided by our technology enabling a trimming of dimensions, leading to significant cost savings.

Figure 9. Left: The approach that mi2 factory takes for supporting customer device design with its energy filter for ion-implantation. Right: A 5 µm-deep p-column created in SiC using an energy filter for ion-implantation.

It’s of little surprise that there has been a consistent drive toward the use of wider bandgap materials for power electronics. After all, the wider the bandgap, the greater the breakdown field, opening the door to making devices with a higher breakdown voltage for the same material thickness.

However, nature is not always that generous. Typically, a move to a wider bandgap is accompanied by more challenging doping, along with difficulty in making high-quality native substrates. Judged in these terms, gallium oxide appears to offer a sweet spot beyond SiC and GaN.

10 cm

To help answer this question, our team at Cornell University has been focusing on the development of Ga₂O₃ vertical power devices. By employing a vertical topology, they are capable of carrying more current per chip area, while taking advantage of the readily available Ga₂O₃ single-crystal substrates. Our goal is to demonstrate the highest unipolar performance that Ga₂O₃ can deliver – it is projected to be far higher than that of SiC and GaN, primarily due to a leap in the breakdown field to 6-8 MV/cm, arising from the superior bandgap. 

A judicious junction

A drawback of Ga₂O₃ is its lack of p-type doping.
Due to this drawback, we incorporate metal-insulator-semiconductor (MIS) junctions in our devices to enhance their blocking voltages. As we’re about to see, the reason behind using of this form of junction is far from trivial.

Let us begin by considering a MIS structure under reverse bias: the semiconductor enters deep depletion near the junction, and a so-called inversion layer results, due to thermal energy within the device promoting electrons from the valence band to the conduction band. This is not good news, as once the inversion layer is created, the entire reverse bias is dropped across the insulator of the MIS structure, leading to catastrophic failure of the insulator and thus the power device. The only option for preventing this catastrophe from taking place is to evacuate the resulting minority carriers quickly. In our case, that means evacuating the holes in an n-type semiconductor.

A key figure-of-merit in this process is the time constant associated with the inversion process (as can be seen in Figure 1, this characteristic is governed by the bandgap).

For semiconductors with a small-bandgap, such as silicon and GaAs, at room temperature an inversion layer forms within seconds or minutes; and at elevated temperatures, where a power device often operates, this time is far shorter, as the time constant plummets by several orders of magnitude. So, in silicon and GaAs devices, a proper p-type contact is needed to sweep out the holes that are generated by either thermal generation or impact ionization. 

In sharp contrast, there is almost never any need to worry about evacuating holes out of Ga₂O₃, so long as the semiconductor is sufficiently pure, and no optical absorption or impact ionization takes place to generate holes. Armed with a sizable bandgap of around 4.5-4.7 eV, Ga₂O₃ effectively suppresses the formation of an inversion layer; and devices made from this oxide will be packaged, preventing absorption of external light.

In fact, for Ga₂O₃, the electric field required for impact ionisation is so high that it can hardly be supported by a true insulator. Even if impact ionisation happens, the generated holes are highly localized, due to the polaron effect and the super flat valence band. This makes it very difficult to evacuate these holes, and the best way forward is to suppress their formation in the first place.

Based on the arguments that we have just presented, we are pursuing an architecture that employs a MIS-junction for voltage blocking and avoids a p-n junction. The significance of the time constant associated with inversion layer formation in a MIS structure is not widely known. However, it is another important virtue of wide bandgap and ultra-wide bandgap semiconductors.

Adding trenches

We have focused our efforts on the development of a Schottky barrier diode. This device is capable of a fast switching speed, due to unipolar operation, but it is compromised by a lower breakdown voltage and a higher leakage current. To address both of these drawbacks, we engineer a charge-coupling mechanism around the Schottky contact. The result: a trench-MIS barrier Schottky diode (see Figure 2), a device that effectively reduces the electric field near the top Schottky contact.

Simulations of a form of our devices, which has a fin channel width of 1 µm and a trench depth of 1.5 µm, reveal the electric field profile when the diode is blocking 2.44 kV – this is the highest breakdown voltage we have achieved so far. According to these calculations, the charge-coupling mechanism reduces the electric field near the Schottky contact to below 1 MV/cm. Due to the trench structure, termination of the electric field is predominantly to the metal at the sidewall, rather than to the top Schottky metal. In contrast, in a regular Schottky barrier diode that does not gain the benefit of the charge-coupling effect, the surface electric field is 4 MV/cm. This value is so high that it leads to an unacceptably-high leakage current density.

Another benefit of our architecture is that it naturally offers field-plating at the edge of the device, thereby reducing field crowding at the Ga₂O₃ edge structures. As the insulator must sustain a high electric field, there is a need for a dielectric material with a high breakdown field and a high dielectric constant, E. Fulfilling these requirement is Al₂O₃, which we add by atomic layer deposition. An additional merit of Al₂O₃ is its sizable bandgap, leading to a sufficiently large conduction band offset with Ga₂O₃ that supports suppression of the tunneling current through the MIS-junction.

We produce our diodes on (001) oriented epitaxial wafers. They are produced by Novel Crystal Technology using HVPE. The drift layer, which has a net doping concentration of around 2×10¹⁶ cm^-3 and a thickness of 10 µm, is designed for making devices capable of blocking 3 kV.

To investigate the influence of the fin geometry, we have produced our portfolio of diodes with fin channel widths ranging from 1 µm to 8 µm. The narrower the fin, the greater the reduction in the surface electric field, and thus the lower the expected leakage current density.

We form our trenches with dry-etching, using metal mask patterns. With our etching recipe, we are able to realise smoothly curved trench corners, which are seen in cross-sectional scanning electron microscopy images (see Figure 4). The smoothness of the corners helps to reduce field crowding, an issue prevalent in devices with sharp corners. After forming the ohmic contact on the backside of the wafer, we add Al₂O₃ with atomic layer deposition, before creating openings on top of the fin channels for the Schottky contact. This contact is formed by evaporating nickel, then sputtering titanium and platinum, to create metal coverage on the sidewall of the fin channels.

Trimming leakage, boosting voltage

As expected, our trench Schottky barrier diodes turn-on at 1.25 V, a figure similar to that for a regular diode (see Figure 5). We find that the differential on-resistance of the trench diodes is governed by the ratio of the fin area to the total device area. When this figure is 50 percent, the trench Schottky barrier diode has a specific on-resistance of 10 mΩ cm2.  In comparison, in a regular Schottky barrier diode this figure is just 7 mΩ cm2. The higher figure, stemming from the restricted current path within the fin channels, is the price to pay for the superior reverse blocking capability, which we will come to later on. Note that the increase in on-resistance is not fixed, and may be minimized by upping the fin area ratio and increasing the effective electron mobility in the fin channel. 

The hit in the on-resistance is out-weighed by the improvement in the reverse characteristics (see Figure 6 for the reverse current-voltage characteristics of the trench diodes). We have found that compared with regular Schottky barrier diodes, our trench-based variants have a lower leakage current and a higher breakdown voltage. Our measurements also show that the narrower the fin, the lower the leakage current, due to an increase in the charge-coupling effect. Due to this, 1 µm fin channel devices have the lowest leakage current density.

Our fabrication process is yet to be optimised, and there is a certain degree of non-uniformity in the leakage current. In several 1 µm and 2 µm channel devices where the parasitic leakage current is minimal, the leakage current is below our measurement noise floor of 1 µA/cm², even at voltages exceeding 2 kV. Such a low leakage is highly beneficial, because it translates into a trimming of off-state power loss.
Even when operating at 2 kV, our low leakage devices can have a power loss on the order of mW/cm². This is very low – to put this figure in perspective, the reverse blocking voltage in commercial kV-class Schottky-based devices is typically specified at a leakage current density of around 1 mA/cm².

It is possible the commercial devices could sustain even higher voltages than the specified blocking voltage without destructive breakdown. However, operating in this regime would increase their leakage current and induce a high off-state power loss. In other words, the full voltage-blocking capability of the material may not be fully utilized due to the constraint imposed by the leakage current. By cutting the leakage current, we will be able to probe the intrinsic voltage handling capability of the material. Understanding the fundamental limit of Ga₂O₃ is essential in our push toward understanding the practicality of devices made from ultra-wide bandgap materials.

The benefits of a narrower fin are not limited to a reduction in leakage current, but extend to an increase in breakdown voltage. This is highest in our diodes with a 1 µm channel, which have a breakdown voltage of 2.44 kV.

To understand this trend, we have simulated the electric field profile at reverse bias for all our fin widths. These calculations reveal that due to field crowding, the electric field peaks at the trench bottom corners within the device’s active region. In narrower channels, the field peak is smaller, due to a reduction in space charge. Higher field peaks are best avoided, as they impair the breakdown voltage.

According to our simulations, for all widths of fin, the peak electric field in Ga₂O₃ hits 5.9 MV/cm at the diode’s breakdown voltage. This suggests that all our diodes, regardless of their fin width, break down at the trench corners. So, to realise high blocking voltages, smooth corners must be used alongside narrow fins. However, note that even with our latest un-optimised design, the highest parallel-plane electric field is 4.3 MV/cm, a value unreachable in SiC and GaN. 

From diodes to transistors

A parallel effort of ours is the development of vertical fin channel transistors. Using a similar architecture to that of our diodes, we have fabricated the first normally-off transistor with a breakdown voltage higher than 1 kV. This result, reported last year, came from a transistor with a figure-of-merit exceeding the silicon unipolar limit.

Since then, we have increased the breakdown voltage of our normally-off transistors to more than 1.6 kV, while maintaining excellent on-resistance. As our vertical fin channel transistor shares many similarities with our trench Schottky barrier diodes, the insights that we have obtained to the device physics of these trench diodes, and also the process optimisation for this device, can be directly applied to our transistor efforts.

Marching on

At last December’s International Electron Devices Meeting (IEDM), we reported results for our trench diodes, showing that these devices set new benchmarks for breakdown voltage and the Baliga’s figure-of-merit in vertical Ga₂O₃ power devices. Pulsed measurements on our diodes with a 2 µm fin channel produce a Baliga’s figure-of-merit of 0.45 GW/cm². These devices surpass the silicon unipolar limit (Figure 8), but are yet to reach the SiC limit.

Analysing the on-resistance indicates that in our latest diodes, the effective mobility is much lower than expected. We attribute this to either un-optimised surface treatments or the starting wafer quality.

If we were able to realise a mobility of 150 cm² V^-1 s^-1, which has been reported in lightly-doped Ga₂O₃ (~10¹⁵-10¹⁶ cm^-3), the on-resistance of our trench diodes would fall by a factor of three to just 3 mW cm², leading to a projected figure-of-merit very close to the unipolar limit for SiC. Such a mobility is not pipe dream, given that the measurements for the highest room-temperature mobility in ß-Ga₂O₃ are around 180 cm² V^-1 s^-1.

Today sales of SiC are rocketing, with GaN not far behind. This demonstrates that wide bandgap devices are starting to fulfil their promise. Next on that list will be Ga₂O₃, which is now making rapid progress. While the lack of native p-type doping is hampering the adoption of some conventional designs, by turning to building blocks such as MIS-junctions, we have shown that functional power devices can be made that deliver good performance. It is clear that backed up by melt-grown high-quality native substrates, Ga₂O₃ is able to deliver power devices with unprecedented unipolar performance and mass-production capabilities.

What is the perfect source of light? Surely, it is one that waste no energy in producing photons that span the deepest violets to the near infra-red, much like the visible rays from the sun. Judged in these terms, the emission from solid-state sources that combine the output of red, green and blue LEDs is encouraging. However, there is still much room for improvement.

Consider the blue and green sources, made from nitride-based LEDs that feature GaInN quantum wells. For these devices, performance is pegged back by three phenomena: droop, the gradual decrease in efficiency as the drive current increases; the green gap, the gradual decrease in efficiency as the indium content in the multiple-quantum-wells rises, to push emission to longer wavelengths; and the electrical potential drop, which leads to dramatic increases in the voltage that must be applied to provide an increase in the driving current.

Addressing all three of these would lead to a dramatic improvement in the quality of the LED light source. It would allow it to operate at a higher efficiency, while delivering a strong spectral output across the entire visible spectrum.

Much effort has already been devoted to uncovering the physical mechanisms responsible for the efficiency droop and the green gap. Researchers have considered carrier overflow/spill-over, carrier localization/delocalization, piezo electric fields, and asymmetric carrier distributions in multiple quantum wells, and tunnelling leakage currents. Many of these investigations have concluded that an increase in a non-radiative recombination process is to blame for the declines in efficiency with higher current densities and longer wavelengths.

Meanwhile, the numerous studies on the electrical potential drop have tended to focus on either current crowding caused by a lateral structure, an insufficient contact potential barrier between the metal and the semiconductor, a high magnesium-acceptor activation energy, or a heavy effective mass for the hole. Often, the problem has been thought to be due to the ohmic potential drop. 

Our team at Akasaki laboratory, Meijo University is taking a different approach to trying to understand the limitations of GaN-based LEDs. We are less concerned with an explanation for droop, potential drop, and the green gap, and have instead set ourselves the goal of understanding the recombination and transport process inside and outside multiple quantum wells, and how this relates to the inefficiencies withiin the LED.

It is well-established that a lower value for the internal quantum efficiency occurs when fewer electrons that are injected into the quantum well are converted into photons. When the internal quantum efficiency falls, this can account for the green gap and the efficiency droop – and it can also be an indirect cause for the electrical potential drop. So, it is clearly important to understand the internal quantum efficiency of the LED, as this can aid the development of artificial white-light sources that take efficiency to a new level.

We have developed an accurate understanding of the internal quantum efficiency of the LED by beginning with an examination of the carrier transport and recombination processes inside the device, using an energy-band diagram (see Figure 1). There are essentially three parts to carrier transport: diffusion-injection from n- and p-bulk layers into the multi-quantum well active region; space-charge limited drift-loss to the opposite bulk layer, due to carrier overflow or spill-over; and leakage currents, arising through the surface defect and the tunnelling leakage current through threading dislocations.

Of these three, the only carrier transport process that has the possibility of leading to light generation is that of diffusion-injection into the multiple quantum wells. Once carriers are in this active region, they may either undergo the non-radiative, heat-generating processes of Shockley-Read-Hall recombination via an internal defect and Auger recombination, or they may emit light via bimolecular recombination. So, in short, the only process that leads to light generation is diffusion-injection into the multiple quantum wells, followed by bimolecular recombination.

To arrive at a deep understanding of the internal quantum efficiency, it is essential to examine the coefficient of each recombination process. As shown in Figure 1, the carriers that are inserted into the multiple quantum wells from the n-type and p-type layers lose their energy through each recombination process. In general, up until now, simply A, B, and C coefficients have been used to express the various processes in the form of the terms, An, Bn², and Cn³, that are united in what is known in the LED research community as the ABC model. Within this framework, the A, B, and C coefficients are considered to be fixed in value, and independent of the carrier density.

Varying coefficients

However, our research reveals that this approach is fundamentally flawed. That’s because the ABC coefficients are not fixed, but have great dependency on the drive current and the carrier density (see Figure 2). For all three coefficients, values rise with carrier density, before peaking and then declining substantially.

We attribute the rising value of the ABC coefficients to the quantum-confined stark effect and the carrier screening effect. Behind the subsequent fall is the high-level-injection in A, and phase-space filling in B and C. Ignore this and treat the ABC coefficients as constant, and there is the danger of failing to understand the actual phenomena within the LED.  

To gain a greater insight into the two efficiency degrading issues, it is critical to be able to measure the internal quantum efficiency of the LED as a function of drive current. Recently, we have developed a highly reliable way to do this, deriving a value from dependency of the general ABC coefficients.

Our approach is to determine the absolute value for the internal quantum efficiency from one of the properties of the ABC coefficients – that they have inflection points at the same carrier density. We also draw on the mathematical model, making use that the differential of the radiative current and non-radiative current is constant only at the driving current where ABC coefficients have inflection points.

Using this approach, our measurements on blue and green LEDs that were made by our collaborators at Meijo University have enabled us to produce plots of light-output-power as a function of driving current and applied voltage (see Figure 3 (a)). As expected, the light-output-power of the green LED is generally lower than that of the blue LED. Also note that at high currents, the electrical potential drop – that is, the slope of the current-voltage curve – is higher for the blue LED than its green cousin.   

Using our approach, we have also plotted the internal quantum efficiency as a function of drive current. As expected, these graphs illustrate two of the biggest weaknesses of GaN LEDs, namely efficiency droop and the green gap. It is also evident that the drop in internal quantum efficiency is behind the lower light-output-power of the green LED, compared with its blue cousin. Clearly, the goal for the LED community is to develop a device that has a small electrical potential drop, alongside an internal quantum efficiency that is high, even at high drive currents and longer wavelengths.

To examine the three efficiency degrading issues in more detail, we have delved deeper into the LED’s carrier recombination and transport dynamics. While doing so, we have made sure that we have investigated the recombination coefficients as a function of current for each sample.

Recently, we reported that one way to determine the recombination coefficient as a function of drive current is to combine the results of the how the: differential carrier lifetime, which is determined from impedance measurements, varies with drive current; with the result of plots of the internal quantum efficiency for different currents. Using this method, we have measured the recombination coefficients as a function of current for blue and green LEDs (see Figure 4(a) and (b)).

Our measurements show that for both the blue and the green LED, the B coefficient, which is dependent on the carrier density, varies with current in the manner predicted by theory. That is, the value for B initially rises with current, before continuously falling after it peaks. Note, however, that there are differences between theory and measurement in the value of B, and the rate of its change.

Comparing blues and greens  

Comparing the blue and green devices reveals that the value of B for the green LED is about ten times smaller than that of its blue sibling, and its degree of decrease at high current is more severe. However, for the blue LED this coefficient decreases rapidly in the non-radiative carrier lifetime high-current region, while the green emitter does not exhibit such a drastic change. Note that for both the blue and green LEDs, the absolute value of non-radiative carrier lifetime at high-current region are similar to each other. That is, the non-radiative process is not the primary cause of the green gap.

Armed with these insights, we have searched for the reason behind the similarities and the differences in the carrier recombination and transport characteristics of the green and blue LEDs. We were also keen to discover how these characteristics would impact LED performance, and what their relationship is with the aforementioned three efficiency degrading phenomena.

Our efforts have given us a new insight into the behaviour of both blue and green LEDs. For blue LEDs, when driven at a low current, the carrier recombination rate is considerably larger than the carrier injection rate. In this regime, every injected carrier recombines, losing its energy inside the multi-quantum well, which has a carrier density determined by the quasi-Fermi level (see Figure 5(a)).

As the current is cranked up, the ABC coefficients gradually decrease, and the increase in the recombination rate fails to keep pace with the increase in the injection rate. Consequently, there comes a time when the carrier injection rate exceeds that of the carrier recombination rate.

At this point, carriers start to gradually accumulate inside the multi-quantum well. In some cases, they even show the same characteristics as those of the hot carrier. If they do, they acquire enough energy to overcome the barrier and escape from the wells to the opposite layer. This spill-over, or overflow, results in efficiency droop (see Figure 5(b)). For the hot carriers that accumulate inside the wells, the result is a space-charge, with current flowing in the form of a space-charge limited drift-leakage current that causes the electrical potential drop (see Figure 1 and Figure 3(a)). So, the efficiency droop and the electrical potential drop are interconnected phenomena in blue LEDs, both caused by a decrease in the recombination coefficient.

The behaviour of the green LED differs from that of the blue, due to the high indium content inside the multi-quantum well that causes alloy fluctuations, resulting in potential fluctuation and carrier localization. When this type of device operates at a low drive current, carriers do not stray far from the low potential area. Operating in this regime, the effective recombination volume of the green LED is smaller than that of its blue cousin (see Figure 6(a)).

Like the blue LED, the ABC coefficients of the green LED decrease gradually with increases in current. Due to this, there is a point at which the carrier injection rate of the green LED exceeds the carrier recombination rate, and the accumulated carriers exit from the localization centre. However, the key difference with green LEDs is that the carriers that exit the localization centre lose their energy in additional Shockley-Read-Hall recombination when inside the wells, due to the high density of non-radiative recombination centres inside this active region.

Judged in terms of the non-radiative carrier lifetime, there is just a small difference between the blue LED and the green LED (see Figure 4). But the value for the B coefficient, which is a function of the carrier density, is about ten times smaller for the green LED than itsblue cousin. This implies that the difference in internal quantum efficiency (see Figure 3) – that is the green gap – is mainly determined by the difference in the B coefficient.

Why should the B coefficient vary so much between the blue and green LEDs? It is due to the complex interaction between: the quantum-confined Stark effect, which is caused by the relatively strong piezo electric field; and the decrease in the density of state of active region, resulting from the potential fluctuation followed by the decrease in the quantization dimension for the green LED. The quantum-confined Stark effect drives apart the hole and electron wave-functions in real-space, while the localization results in the separation of the hole and the electron wave-functions in k-space. The upshot is a dramatic fall in the carrier-density-dependant B coefficient, which accounts for the green gap.

Our work shows that efficiency droop is caused by the decrease of the ABC coefficient, triggering space-charge limited drift-loss that makes an electrical potential drop, while the green gap is caused by the decrease of B itself. While the non-radiative processes caused by them are different, the cause of both these phenomena is the same: the degradation of the B coefficient.

We have studied the three biggest impediments to high-efficiency LEDs: the efficiency droop, the green gap, and the electrical potential drop. Our work breaks new ground by examining all three of these maladies from the viewpoint of the reduction of recombination inside the multi-quantum well. All three impediments are, in principle, identical. Therefore, they can be simultaneously addressed by improving the radiative recombination among the recombination processes within the wells.