Ask Richard Eden, senior market analyst at Omdia, what single development has had the biggest impact on the SiC market in recent months, and his answer is the launch of Infineon Technologies’ CoolSiC CIPOS Maxi: the world’s first SiC IPM. This 1200 V integrated power module comprises a six-channel, silicon gate driver with six 1200 V CoolSiC MOSFETs, and signalled the end of the power semiconductor company’s roll-out of CoolSiC products in 2020.

As Eden puts it: “Infineon is a juggernaut in power semiconductors, especially in discrete and modules... the IPM was anticipated a while ago and we always thought it was the logical thing to do.”

“We will see more companies introducing SiC IPMs – someone like On Semiconductor could be next – but Infineon was the first company to get this finished and released,” he adds.

According to Eden, the IPM offers the benefits of SiC MOSFETs, over silicon MOSFETs and IGBTs, but with the ease of having a co-packaged gate drive IC. Critically, the move could see IPMs being used in both domestic and more demanding industrial applications.

But 2020 wasn’t all about Infineon. Other key SiC developments centre on new generations of existing products, such as ST Microelectronics’ fourth generation 750 V SiC FET platform, as well as increasing production capacities from Rohm Semiconductor, X-Fab, II-VI, and of course Wolfspeed, the Cree company. Indeed, Eden reckons that Wolfspeed’s Mohawk Valley Fab in New York state – set to be the world’s first 8-inch SiC fab with production scheduled for 2022 – will be a game-changer.

“Many other semiconductor companies buy Wolfspeed wafers, so this facility could trigger the transition from six- to eight-inch wafers in the industry,” says Eden. “Also, many companies currently using six-inch wafers are working with old, eight-inch silicon wafer equipment, so the move to the larger wafer size might not be too difficult.”

“Yields will be poor with these eight-inch wafers initially, and it will take a year or two to get them back up with this larger wafer size,” he adds.

Following the concerted efforts to ramp SiC wafer production, twinned with the many industry supply agreements, Eden believes the SiC wafer supply shortages that plagued the industry from 2017 to 2019 are no longer an issue, for now. Analyst forecasts predict strong market growth, which he reckons could strain future supply levels. “I know companies such as Rohm, Cree and II-VI are trying to add capacity beyond when they think they will need, but we will have to wait and see,” he says.

Eden also reckons that the current pandemic hasn’t affected SiC market demand significantly. As he says, factories temporarily closed during the first major lockdown of 2020, but have since recovered with the market having also grown slightly. “The silicon semiconductor market was affected more severely than the wide bandgap segment,” he says.

Market leaders

Earlier this year, and for the first time, Eden, with Omdia, ranked SiC semiconductor supplier market shares, with intriguing results. For the overall power discrete and module markets in 2018 and 2019, Wolfspeed lead the way, followed by STMicroelectronics, Infineon, On Semiconductor and Rohm. But individual markets tell a different story.

For the SiC rectifier device market alone, Wolfspeed had a huge lead in 2018 and 2019, capturing more than 40 percent of the market in each year. “Wolfspeed has this lead as it is the oldest incumbent supplier of SiC discretes and has been making these for around 20 years,” highlights Eden.

Infineon, Rohm, STMicroelectronics and On Semiconductor are ranked from second to fifth, respectively, again largely thanks to longevity. “Rohm is the newest supplier here, but is now established as it was the first company to mass produce SiC MOSFETs in 2010, and developed SiC rectifiers around the same time,” says Eden.

For the SiC power MOSFET markets, STMicroelectronics takes pole position, which according to Eden, is thanks to the company’s significant contract to supply devices to battery electric vehicle maker Tesla. Yet despite its Tesla-dependence, he expects ST to maintain its lead.

“Currently at fourth place [following ST, Wolfspeed and  Rohm] Infineon would surely be higher in the rankings if it hadn’t focused on developing SiC JFETs ahead of SiC MOSFETs during the mid-2010s,” he adds.

The full SiC  and hybrid SiC module markets are quite different, with Mitsubishi Electric and On Semiconductor leading each market in 2019, respectively. Germany’s Vincotech, Infineon and Wolfspeed also feature highly in these markets with China players, StarPower Semiconductor and CRRC Times Semiconductor also creeping into the module supplier top five. According to Eden, many module suppliers tend to buy in power transistors and assemble these in the modules, rather than manufacture the chips themselves. Also, going forward, he expects to see more China-based players enter module markets.

“StarPower is currently the largest Chinese power module manufacturer and is still quite small in the overall market,” he says. “But there are other Chinese companies making power modules, such as Nanjing SilverMicro Electronics, and they will become more prevalent following the Chinese government drive to use silicon carbide for electric vehicles and industrial applications.”

Eden doesn’t believe that the US-China trade tensions have particularly affected SiC markets. But as he adds: “There is a trend for Chinese companies to want to buy Chinese products, as strongly influenced by the Chinese government.”

So what does Eden reckon will come next for the SiC market? For the time being, he expects that SiC technology will happily co-exist with silicon and GaN, capturing market share from silicon throughout this decade. However, beyond this timeframe may bring change. “Right now, the GaN market is behind the SiC market but ultimately, by the 2030s and 2040s say, GaN might end up having the larger market share than SiC.”

Indeed, thanks to wafer costs, Eden reckons GaN will always offer a cheaper alternative to SiC. He highlights how a silicon wafer currently costs around $10, a GaN-on-silicon wafer costs around $25, while SiC wafers currently come in at up to $1000 each.

“The substrate is the determining factor for device cost, and I think that once yield, design and other challenges are resolved, GaN devices are going to be cheaper than SiC devices,” says Eden. “Silicon carbide is potentially a stop-gap during the 2020s until gallium nitride is perfected – and then this technology will have a bigger market for discrete power semiconductors and power modules.” However, at the end of the day, silicon, SiC, GaN and, potentially, Ga₂O₃ semiconductors will co-exist, each occupying market niches, depending on the cost and performance benefits that each offer.

Most of the energy consumed in computing systems is not in the computation, but in moving data, and the longer the distance, the greater the challenge in terms of energy and density.  At longer length scales, fibre optic links have replaced copper, but at short distances the significant amount of energy required to convert data back and forth between photons and electrons makes optical interfaces prohibitive.

Although it may raise a few eyebrows, at these shorter length scales, optimized optical emitters derived from GaN microLEDs could be a promising candidate for optical communications by leveraging their success in the display industry. Such a move could transform the $400 billion computer hardware industry and enable entirely new architectures for parallel computing, machine learning, and processors.

Within the semiconductor industry, the days of enjoying rapid rates of progress on multiple fronts are long gone. There has been little increase in chip clock rates during the last two decades. There are also limits on the number of IC package input and output pins. Consequently, almost all high-performance chips utilize high-speed Serializers/De-serializers – known as SerDes – for input/output on the periphery of the die. Their role is to dramatically increase the bit rate compared with on-chip clock speeds so that all the information can be to squeezed through a limited number of pins. This takes energy, real estate, and chokes data flow – and the situation is only going to get worse with future system advances being realised primarily through new architectures that interconnect more chips rather than improvements in raw transistor performance.

By packaging chips on silicon interposers with a far higher density of lines, electrical data-pipes can be connected to very wide busses and operate close to the clock speed of the chips. However, for reasons already outlined, a high density limits the reach, with chips typically having to be placed edge-to-edge. It is common to co-package high-bandwidth memory chips adjacent to the processor (see the leftmost illustration in Figure 1), and communicate over a bus that is typically about 1000 lanes wide, running at only 1 or 2 Gbit/s. Note that Intel’s AIB bus, TSMC’s LIPINCON bus and the Open Compute Project BoW busses are all wide and slow, with hundreds or thousands of lanes, each operating at 1 Gbit/s to 16 Gbit/s.

Different optics

It has been known for decades that even very short optical interconnects promise significant power and density advantages over electrical interconnects. This advantage, based on ‘quantum impedance transformation’, hinges on the use of low-capacitance, high-quantum-efficiency optoelectronic devices. Unfortunately, despite decades of effort, such sources are still to emerge for short links. Edge-emitting lasers, VCSELs, quantum-well modulators and silicon photonics modulators all fall far short of what is needed for practical short optical interconnects (from 1 mm to 10 m). A litany of issues has prevented success, including a high drive power, large size, poor high-temperature performance, expensive and bulky packaging, and a poor yield.

There are several options for moving the light between chips. This can be carried out with monolithically fabricated waveguides on an interposer or with various kinds of multicore and imaging fibres. The use of high-density multicore fibres is well established, having been employed for decades in imaging applications, and used in borescopes, medical endoscopy and other ‘display’ applications.

Operating in the visible spectrum with optimized CROMEs and CMOS-compatible photodetectors that are integrated with amplifiers, virtually all capacitance is eliminated. We estimate that such links can deliver an energy efficiency below 100 fJ/bit and deliver a multi-Tbit/s throughput at a density in excess of 10 Tbit s^-1 mm^-2.

There has already been considerable interest in high-speed visible wavelength LEDs for free-space optical interconnects and ‘LiFi’, where LEDs are used to generate ambient lighting and transmit data. Such LEDs have a range of criteria to fulfil, needing to be both very efficient and fast. But in a chip-to-chip application considerations are markedly different, and one can trade off quantum efficiency for speed. In fact, the benefits of doing so are tremendous. By optimizing the device’s doping, quantum well structure, device design, and other features, CROMEs can be fast enough for very high-density, high-performance IC interconnects. We have demonstrated CROME-based links with wide open eyes at even 10 Gbit/s (see Figure 3), a speed previously accessible only with high-speed lasers or modulators. 

Figure 4 shows some CROME experimental results. At very low current densities the 3dB bandwidth reaches about 2 GHz (or around 4 Gbit/s for on-off modulation). Good link performance is realised at drive currents of a few tens of microamps. This allows the power consumption per bit to be far lower than that for lasers. Note that even very small VCSELs, the most energy-efficient lasers, typically have a threshold current of a milliamp.

Using blue light for data transmission is incredibly advantageous at the receiver. Silicon is a nearly ideal material for detecting blue light, with an absorption length of just 0.2 mm. This enables CMOS-compatible fabrication of receivers with integrated photodiodes. These photodiodes with very low parasitic capacitance (less than 10 fF) allow use of innovative, simplified transimpedance amplifier designs, enabling receiver power dissipation of below 50 fJ/bit. Such a low power is not possible with ‘typical receivers’, which are hampered by a much higher capacitance and greater complexity.

Perfecting the package

We use highly multimode fibres and waveguides to realise efficient optical coupling to the sources and detectors. This relaxes alignment tolerances. One of the merits of this approach is that it allows us to select between a variety of useful packaging architectures, each with a different range of benefits.

Our fibre-based links are optimized for longer interconnects, spanning distances from 10 cm to 10 m. These links transfer data between chips and multi-chip modules at the board, shelf and rack levels. Transmitters are connected to receivers using high core-count or imaging fibre (see Figure 6).

A typical imaging fibre has hundreds or thousands of cores, each with a diameter ranging from 2 μm to 20 μm. Manufacture involves standard ‘stack and draw’ optical fibre fabrication techniques. Optical channels can be sent through this fiber on a square grid with 20 μm centre-to-centre spacing, with each carrying 4 Gbit/s. This gives an areal interconnect bandwidth density of 10 Tbit s^-1 mm^-2. Sending 256 of these channels through a fiber provides a total throughput of 1 Tbit/s. As such a fibre is less than 500 μm in diameter, multi-fibre ribbons and cables capable of carrying more than 10 Tbit/s are very compact and flexible. That’s in dramatic contrast to bulky DAC twinax.

Since all our processes are fully CMOS compatible, interconnects can also be made directly from the surface of a large complex IC. This direct ‘optical pin-out’ enables ultra-dense, ultra-low-power optical interconnects directly from anywhere on an IC. Operating with an interconnect density of 10 Tbit s^-1 mm^-2 and an energy per bit of just 100 fJ/bit, these links could provide outputs and inputs for a 100 Tbit/s (bidirectional) switch IC from a 20 mm² footprint, and a power consumption of just 20 W. 

Compelling credentials

The strengths of our CROME interconnect technology go well beyond performance. They also fulfil all the other requirements for practical high-volume products: they have a high reliability, they deliver excellent high-temperature operation, they are low in cost, easy to package, and they are compatible with existing high-volume manufacturing and test capabilities.

Our links’ optical interfaces are formed from a variety of technologies that are used in very high volumes in different applications. From a manufacturing perspective, CROME arrays can be thought of as very small GaN microLED displays. As regular readers know, GaN is manufactured in huge volumes for solid-state lighting and power devices and is becoming increasingly important for displays. Production of this device is underpinned by a massive ecosystem that supports high volume, low-cost manufacturing. In general, GaN is a far more reliable and robust material system than other III-Vs, such as GaAs and InP, due to its excellent high-temperature performance and insensitivity to defects. Unlike devices made from other III-Vs, those built from GaN can operate at high temperatures, such as 150 °C, with extremely low failure-in-time rates.

We are able to draw on existing high-volume manufacturing processes used in the lighting and display industries for the mass transfer of thousands to millions of CROMEs from a sapphire source wafer to a target silicon CMOS driver wafer containing transceiver circuitry. Compared to display requirements, the data interconnect is very undemanding: there are fewer than tens of thousands of lanes, and the application is insensitive to colour and brightness variations, both critical concerns for display makers. Another positive for us is that some redundancy can be built in with spare channels, which is also done in wide slow electrical busses. Our transceiver circuitry and our photodiodes are manufactured using standard CMOS. We can use older process nodes, thanks to the modest link speeds. For coupling we can use polymer micro-optics, similar to those in smartphone cameras. 

By leveraging all these high-volume technologies, we estimate that the costs of these Tbit/s wide parallel GaN-based links are one to two orders of magnitude lower than the cost of other high speed serial optical link technologies, such as pluggable optical transceivers, board mounted optics, or even silicon photonics co-packaged optics aimed for datacenter and computing environments. Although our technology is multimode and limited to 10 m reaches, it clearly promises to have an important role to play in advancing the performance of computing systems.

WHILE THE PANDEMIC has taken its toll on all of us, it’s been hardest on the poor. Those with bigger salaries are less likely to have lost their jobs, and if they’ve had a chance to invest any spare cash, they are probably enjoying a good return.

Canny investors will have considerably strengthened their financial position over the last year or so by buying shares in technology companies. As a glance at our annual Shareprice Leaderboard shows, over the 12 months up to the end of April 2020 the tech-heavy NASDAQ climbed by just over 60 percent, while some companies in our industry have fared even better (see Shareprice Leaderboard below). Topping our list is Cree, thanks to a valuation that has leapt more than three-fold. Substrate maker AXT is not far behind, and even third-placed II-VI has delivered a return over this timeframe of around 140 percent. 

Champion Cree

Cree’s soaring share price reflects the success it has had in transforming its business. It has now sold-off its LED chips and lighting businesses, which brought declining returns over the last decade or so, and has turned its attention to making SiC substrates, SiC power devices and GaN-on-SiC RF products. Marketed through the moniker Wolfspeed, sales of these products are ramping, and could continue to do so throughout this next decade and beyond as the company executes a massive capacity expansion programme to produce higher volumes more efficiently.

The company still has a long way to go along this road. Sales of its revamped portfolio are growing, with revenue for the third fiscal quarter of 2021, ending on 28 March, netting $137.3 million. This is above guidance, an 8 percent increase sequentially, and up 21 percent compared with the equivalent fiscal quarter of the previous year. However, due to a combination of Covid-19 safety measures and a temporary increase in higher factory costs, gross margins are heading in the wrong direction, having fallen 0.4 percent sequentially, to 35 percent. This will have contributed to the loss for the latest fiscal quarter, which is $24.7 million, according to non-GAAP accounting.

During a third fiscal quarter earnings conference call, held on 28 April 2021, Cree’s CEO Gregg Lowe offered some insight into the latest trends in the markets where the company’s products serve. “We are seeing more demand in our core automotive and RF markets, as well as additional interest in new areas across energy, industrials, and aerospace and defence,” revealed Lowe. Diversity of deployment is impressive, including devices designed into forklifts, 3D laser printers, air conditioners, motor drives, robotic arms, flying vehicles and a beer truck.

Lowe added that the company’s device pipeline now stands at more than $10 billion, with new opportunities being identified at a rapid pace. In just the last quarter, the company’s sales team secured more than $580 million in design-ins; and over the last five quarters this figure totals $2.5 billion.

Over the next few years, Cree is set to benefit from the $2 trillion infrastructure plan recently unveiled by the US administration. Within the plan, $100 billion is dedicated to increasing broadband access, with a special emphasis on 5G infrastructure. Remarking on this, Lowe commented: “This development, combined with strong sales of 5G smartphones during the pandemic, underscores how 5G is continuing to gain momentum and offers a global opportunity in the years ahead.”

Also included in the infrastructure plan is significant funding for electric vehicles, including sales rebates, tax credits and charging stations. “We anticipate this will have a significant impact on the adoption of electric vehicles,” reasoned Lowe. “We are now seeing US automakers make big commitments to ramp their EV efforts. For instance, General Motors and LG Chem recently announced plans to invest $2.3 billion to build a battery cell plant to support the automaker’s efforts to expand its electric vehicles.”

Cree could also benefit from a ramp in electric vehicle production in Europe. On a recent trip to Germany, Lowe had very positive conversations with a number of tier one carmakers, who are struggling with supply constraints associated with silicon chips. He offered them hope, telling them that Cree is going into production with the world’s largest SiC fab, right in the middle of this supply issue. This great timing, which Lowe openly admits is more down to luck than judgement, bodes well for Cree’s future. “[It] is certainly a very nice light at the end of the tunnel for some of these guys as they start placing bets on silicon carbide.”

Until the Mohawk fab is up and running, sales are likely to show a moderate increase, rather than a massive ramp. During the next quarter revenue is tipped to rise to between $142 million and $148 million, with the majority of the increase coming from the power and RF device product lines. A small uptick is also anticipated from the materials division.

AXT accelerates

Throughout most of last year, AXT’s share price hovered at around $5, before leaping to almost twice that in November, and surging as high as just over $15 in late February. The company’s valuation has dropped back a little since then, but sales continue to climb. They leapt from $22.1 million for the second fiscal quarter of 2020 that ended on 30 June 2020 to $25.5 million and $27.0 million in the third and fourth fiscal quarters that followed, and have broken the $30 million barrier in the most recent quarter.

Earlier this year II-VI has launched double-junction VCSEL arrays, targeting next-generation world-facing 3D sensing applications.

This growth is attributed to an increase in sales to chipmakers serving a broad range of markets, from 5G telecommunications and its related technologies to datacentre connectivity, LED-based sensing and display, healthcare monitoring and consumer devices.

Of the $31.4 million netted in the most recent quarter, $23.4 million came from substrate sales and $8 million from the two joint-ventures: BoYu, a manufacturer high-temperature crucibles and tools for OLEDs; and JinMei, a diversified industrial supplier of high-purity materials.

As well as growing revenues, AXT is reducing reliance on its biggest customers. Company CFO Gary Fisher highlighted this welcome move in a call discussing earnings on 28 April, 2021, when he revealed that no customers accounted for 10 percent or more of overall revenue, and the top five contributed just 26 percent to total sales. “Usually, we do have at least one 10 percent customer,” added Fisher. “And usually, the top five customers contribute approximately 35 percent to 40 percent of total revenue.”

Gross margin is on the rise, reaching 36.8 percent in the latest fiscal quarter, up 2.9 percent sequentially and 10.2 percent year-on-year. Thanks to this, plus a favourable product mix and and increasing sales, net profit hit £3.4 million, up $1.3 million sequentially.

During a recent earnings call, AXT CEO Morris Chang discussed sales for all three types of substrate produced: InP, GaAs and germanium.

Shipments of InP are seeing strong growth. “We saw continued strength from 5G and its related technologies,” said Chang, who did not know whether these wafers were for optical connections for 5G equipment, or technologies such as passive optical networks that support 4G and 5G functionality. “But from our perspective, any modernization of telecom infrastructure that utilizes indium phosphide is positive for our business.”

Demand for GaAs substrates has recently increased, due to sales to makers of LEDs and wireless products. For this class of substrate, revenue for the first fiscal quarter 2021 exceeded all quarters since the first fiscal quarter 2018. Sales in the coming quarter will be helped by strong demand by LED makers, but hindered by a softening of sales to those making wireless products.

AXT is continuing to invest in both its InP and GaAs technology. It is developing 6-inch InP substrates and has just unveiled 8-inch GaAs substrates for LED applications. Commenting on the latter, Chang remarked: “This is no longer a test tube laboratory program, because we are now shipping wafers according to our customer specifications. This is a tremendous step for AXT, and we are very proud of our team.” It is hoped that the large substrate size will help to provide scale and efficiency for very high volume manufacture of VCSELs for 3D sensors and LiDAR, and microLEDs for displays.”

For germanium substrates, revenue for the recent fiscal quarter is down slightly. However, growth is expected this year, thanks to a strong satellite market. This should provide a modest increase in the next quarter.

For that quarter – the second fiscal quarter of 2021 – AXT predicts that contributions from germanium, plus growth in InP and GaAs revenues, will propel sales to between $30.5 million and $31.5 million. Profit is expected to be in the range $2.6 million to $3.4 million.  

Third for II-VI

II-VI, third on our Leaderboard, has seen its share price follow the same trend as AXT: broadly flat to last November, climbing to peak in February, and now a little below that high point.

This multi-national powerhouse, with products that include GaAs electronic devices, SiC substrates, laser systems and components for optical networks, claimed several records in its last quarterly results, announced on 9 February, 2021. Quarterly sales broke new ground, hitting $787 million, backlog reached a record $1.08 billion, and cash from operations climbed to a new high of $221 million.

The management at II-VI are very pleased with the integration of Finisar into the existing business. Discussing this in a second fiscal quarter earnings call, held on 9 February 2021, company CEO Chuck Mattera revealed that progress on this front is ahead of schedule: “We are now on track to achieve our $150 million total synergy target in 24 months, or 12 months ahead of schedule. And we are now increasing our three-year total synergy target to $200 million.” This success is helping to strengthen margins and ensure a strong cash flow.

Details of particular product successes were highlighted in the call by Giovanni Barbarossa, who is Chief Strategy Officer and President of the Compound Semiconductor Segment.

Barbarossa revealed that products for 3D sensing increased more than 140 percent sequentially. “3D sensing growth came from shipments of production volumes of VCSEL arrays for multiple end customers, including for front-facing and world-facing applications, as well as for other consumer electronics, and automotive in cabin sensing,” said Barbarossa. According to him, sales of VCSEL arrays should continue to rise as II-VI expands its customer base with additional wins, including in the Android ecosystem and personal computing platforms.

II-VI has devoted much time and effort to building up its 3D sensing products. Back in 2013 it bought Oclaro’s GaAs laser business; three years on it purchased the Anadigics GaAs fab and the Epiworks facility; and in the autumn of 2019 it bought the Finisar fab. 

“When we acquired Finisar some asked us which gallium arsenide fab we plan on closing,” remarked Barbarossa. “Our answer was none because we needed the capacity to gain share and become the market share leader, by offering breakthrough solutions at scale.”

As well as sensing, the VCSELs made by II-VI are targeting LIDAR. Barbarossa is confident of success in this sector, arguing that the company has the broadest portfolio of products in the industry. “Unlike our pure play laser competitors, we have an entire vertical integrated portfolio of both active and passive components, made from our engineering materials that are critical for these next generation LiDAR designs.”

SiC products for power electronics could also help to grow II-VI revenue. Encouraging signs on this front include a purchaser of II-VI’s SiC substrates winning selection by a tier-one automotive manufacturer in Japan.

Another promising portfolio of products are InP-based lasers. Shipments of high-data-rate coherent transceivers are on the rise, adding bandwidth to new and existing networks, and sales are up for 200G and 400G components. “We are also excited to announce that we have just sampled our first 800G transceivers to a large web-scale customer, who has already provided exciting feedback,” added Barbarossa.

II-VI is widening its broad portfolio with the acquisition of Coherent, a manufacturer of a broad range of lasers, including CO, CO₂, excimer, solid-state and fibre sources. II-VI emerged victorious in a bidding war with MKS Instruments and Lumentum during the first few months of this year. The stock-and-cash deal, worth around $7 billion, is expected to close at the end of this year.

Results just in for the third fiscal quarter show that the company continues to thrive, generating a revenue of $783 million and a cash flow from operations of $447 million. For the fourth fiscal quarter, sales are expected to net $752-802 million, with earnings of $98-127 million.

Languishing Lumentum

Footing this year’s table is laser diode manufacturer Lumentum. It’s not that Lumentum has performed poorly – it’s just that its peers have fared better. Over the timeframe considered in the annual Shareprice Leaderboard, Lumentum has seen a rise in its valuation by about 20 percent, while based on a pre-Covid reference point of the start of 2020, the increase in share price is around 17 percent.

Lumentum has been experiencing mixed fortunes. Sales of it VCSELs for 3D sensing applications have been strong, but shipments of telecom lasers have weakened, due to a push-out in 5G deployments. There has also been a sharp decline in sales of commercial lasers, due to weakness within the industrial sector.

While the company’s management may also rue their failure to secure Coherent, market reaction to missing out on this deal has actually been favourable. When news broke in March that II-VI had finally won the bidding war, Lumentum’s valuation climbed by around 5 percent, probably spurred on by a boost to the company’s financial assets – it would now be in line for a termination fee, worth $218 million. 

Very recently Lumentum has released its results for its third fiscal quarter of 2021, ending 31 March. Sales missed guidance, coming in at $420 million, down 12 percent sequentially and below the guidance given in February of $425 million to $440 million. This news didn’t go down well with the market, with shares tumbling 15 percent. 

Company CEO Alan Lowe accounted for unexpectedly low revenue in a quarterly earnings call given on 12 May. He blamed the sales shortfall on China’s roll out of 5G, which is going slower than anticipated, due to geopolitical tensions with the US and shortages of electronic components. Continued delays in 5G fronthaul deployments in China have dragged down third quarter revenue for directly modulated lasers to significantly below year-ago levels. There will be no immediate improvement, with sales of this class of laser for the upcoming quarter expected to be down by more than $20 million year-on-year. “At this time, we expect 5G fronthaul deployments could resume this summer,” added Lowe. “This timing would drive increased demand for our products towards the middle of fiscal ‘22, once customers ramp up and burn through existing inventory.”

Another sector weakening in the short term is 3D sensing. Due to customer design decisions, the global market for 3D sensing lasers is expected to decline between 20 percent and 25 percent during Lumentum’s fiscal 2022. However, during that fiscal year, and the one that follows, laser-based sensing is expected to expand into more applications and markets. Lowe says that this will set the stage for reacceleration of market growth in fiscal 2023.

Although total sales are expected to be sluggish for the next few quarters – revenue for the first half of fiscal 2022 is expected to be down approximately 5 percent relative to the first half of fiscal 2021 – the company is very bullish about its longer-term prospects. Sales for this latest quarter were rich in new and differentiated products that enjoyed double-digit year-on-year growth, and can serve in markets with great prospects for expansion over many years. These products include InP coherent components and modules, next-generation contentionless ROADMs, high-speed electro-absorption modulated lasers and 3D sensing lasers.

Commenting on these opportunities, Lowe remarked: “The computer and machine vision revolutions are in their early days, and we expect 3D sensing and LiDAR capabilities will expand to many more applications in multiple markets.” In his view, there are opportunities in augmented and virtual reality, 3D machine vision for industrial applications, frictionless and contactless biometric security and access control, and automotive and delivery vehicle applications. Another sector with much promise is laser-based material processing, which Lowe says is critical to the manufacturing of the devices that enable the digital transformation and transition to 5G wireless, as well as the production of electric vehicles and technologies for energy storage.

THERE ARE MANY applications requiring a source of deep-UV emission. Radiation in this spectral domain is employed for materials processing, sensing, and disinfection targeting bacteria and viruses, including SARS-CoV-2.

Today, the incumbent source for these tasks is the mercury lamp, which is available in low-pressure or medium-pressure formats. A more promising option, though, is the LED: it is smaller, more robust, and does not require high voltages or employ toxic materials. There is also potential for production costs of this chip to fall, just like they have for its blue and white cousins.

Holding back the deep-UV LED is its low external quantum efficiency, which is limited by poor carrier injection and a low light-extraction efficiency – in short, it suffers from a transparency-conductivity dilemma. Makers of UVC LEDs tend to trade conductivity for transparency by utilising GaN:Mg p-layers for the injection of holes. While a good choice for electrical performance, GaN is compromised by its UV light-absorbing nature. Increasing the aluminium mole fraction in the p-AlGaN layers combats absorption losses, but at the expense of higher magnesium acceptor ionization energies that lead to a significant increase in the resistivities of the AlGaN:Mg layers, and in turn, the operating voltage. Another downside of AlGaN:Mg is that despite much effort, an ohmic contact is elusive. Forming such a contact is challenging, due to the large work function mismatch between UV-reflective metals and the high electron affinity of p-type III-nitrides.

One well-known strength of MBE is that, in contrast to MOCVD, it is well suited to realising very abrupt doping profiles that are beneficial for a tunnel-junction interface. In addition, MBE is capable of very high magnesium doping levels, such as more than 10²⁰ cm^-3; and it can avoid hydrogen passivation of magnesium acceptors and magnesium diffusion during overgrowth of the n-doped layer.

However, despite all these strengths associated with MBE, there is still much merit in trying to develop an MOCVD-based process for producing tunnel junctions. The latter is the dominant manufacturing technology for producing III-nitride LEDs, with processes applied on an industrial scale. What’s more, the use of  MOCVD allows tunnel-junction LEDs to be grown in a single run, eliminating the need for a two-step growth process.

Injection by interband tunnelling

When a tunnel-junction is incorporated into the p-side of a deep-UV LED, this leads to non-equilibrium hole injection via tunnelling (see Figures 2 and 3). Operating in forward bias, such a device produces a tunnelling of electrons from the AlGaN:Mg valence band into the AlGaN:Si conduction band. This process leaves a free hole that is injected into the active region, where it takes part in radiative recombination. The efficiency of this tunnelling may be described by a tunnelling probability.

We have simulated the properties of our LEDs, considering an Al_0.7Ga_0.3N tunnel junction (Figure 2 shows energy band diagrams at zero bias). These calculations included a reference structure with homogeneous and abrupt silicon- and magnesium-doping of 10¹⁹ cm^-3 at both sides of the junction – for this structure, the space charge region is 32 nm wide. When we increase the doping levels to 10²⁰ cm^-3, the width of this region decreases to just 10 nm. Another option for reducing the width of the space charge region is to introduce a polarization-field-enhanced tunnel-junction heterostructure with a GaN interlayer. This modification shortens the width of the space charge region from 32 nm down to 23 nm (see Figure 2 (b)).

Within certain limitations, there is no need to choose between these two options, but rather incorporate both of them. This has a huge pay-off, because reductions in the space charge region deliver an exponential increase in tunnelling probability, and in turn a significant hike in device performance.

Initial emission

Fabrication of our first MOCVD-grown LEDs that feature tunnel junctions involved an in-situ thermal annealing step after the growth of the magnesium-containing layers to activate magnesium acceptors. With this step, acceptor passivation by hydrogen is reduced to negligible levels – according to secondary ion mass spectrometry, the ratio of hydrogen to magnesium atoms is below 10 percent. Device processing is completed with mesa etching, followed by simultaneous deposition of top and bottom V/Al/Ni/Au n-metal contacts and then a rapid thermal annealing of these contacts under nitrogen (see Figure 4 (a) for a microscopic image of our processed tunnel-junction LED, with a TU Berlin logo).

As we expected, our variant with the homojunction has a higher tunnelling resistivity, with high voltages producing low currents. The sibling with the heterojunction produces better results. For that device, on-wafer measurements at a 60 mA drive current produce an output power up to 6.6 mW, corresponding to an external quantum efficiency of 2.3 percent and a wall-plug efficiency of 0.42 percent (plots obtained using a pulsed current are shown in Figure 5 (b)). Encouragingly, light-current and current-voltage characteristics show no indication of carrier leakage or parasitic current paths.

Using a UV-enhanced microscope camera, we have mapped the intensity across the tunnel-junction LEDs. Imaging of our finger-shaped LED mesa, with a thin central metal contact on top, shows emission from the entire mesa area (see Figure 6). The uniform emission highlights homogenous acceptor activation and current injection through the tunnel junction. If our tunnel-junction LEDs were impaired by incomplete activation or issues associated with local injection problems, this would have led to dark areas without any emission.

Deeper into the UV

Our technology is capable of going deeper into the UV than the devices discussed so far, which emit at 268 nm. The fundamental limitation is the bandgap of AlN, which is just above 6 eV – this corresponds to emission at around 200 nm. Success in this domain is not easy, and gets progressively harder with every nanometre further into the deep UV. Reasons for this include: increasing severity of UV absorption; reductions in doping efficiency; limited options for carrier confinement, all issues for such LEDs in general; and lower tunnelling probabilities, resulting primarily from an increase in the tunnel barrier, due to an increase in the AlGaN bandgap and a larger space charge region.

By taking on these challenges, we have managed to expand the spectral range of our MOCVD-grown tunnel-junction LEDs down to 232 nm, a world record for this class of device (see Figure 7). Electroluminescence spectra show a dominant emission peak from the multiple quantum wells, and only marginal parasitic long-wavelength emission from these non-optimized structures.

Plots of current-voltage characteristics highlight one weakness of our device. Its operating voltage is above 15 V, and clearly needs to be improved. Emission power is encouraging, at almost 0.2 mW at 20 mA, helping to deliver a peak external quantum efficiency as high as 0.16 percent. For UV LEDs operating at such ultra-short emission wavelengths, this value – obtained on-wafer – is close to the highest values ever reported. In fact, it is enabled by the highly UV transparent TJ-LED heterostructure that overcomes the transparency-conductivity-dilemma of deep UV LEDs with potential for even more improvements.

The conventional approach to quantifying the efficiency of tunnelling is to use differential device resistivity (this is dV/dj, simply calculated from j-V measurements). So long as the tunnel junction provides the main contribution to device resistivity, this metric offers a solid basis for comparing different tunnel-junction LEDs.

We have compared values for device resistivity versus current density for tunnel-junction LEDs grown by MBE and MOCVD, using data reported by various groups (see Figure 8). Our plot highlights the underlying trend of decreasing resistivity with increasing current density, which occurs over several orders of magnitude and is independent of device design and growth method. One implication is that MOCVD is just as good as MBE for growing tunnel-junction LEDs.

Another benefit of this plot, shown in Figure 8, is that it allows small variations at a fixed current density to compare properties of individual tunnel-junction LEDs. When viewed in this manner, the results highlight the outstandingly low device resistivity of nearly 10⁴ Ω cm² at 2 kAcm^-2 for InGaN-based devices produced at Unipress.

Device resistivity appears to be fairly independent of the bandgap of the tunnel-junction and its growth method, but it is connected to the wavelength. A low resistivity is only realised in GaN- and InGaN-based tunnel-junction LEDs emitting beyond 350 nm. When tunnel junctions employ AlGaN they show higher operating voltages as well as higher differential device resistivities due to lower achievable current densities. However, as well as the work by our team, independent efforts at Ohio State University and CRHEA-CNRS show that when tunnel junctions are formed with an aluminium mole fraction way above 50 percent – this corresponds to a bandgap above 4.5 eV – they offering an alternative approach to carrier injection that combines transparency with conductivity.

Once we have demonstrated high-performance tunnel-junction LEDs at the wafer level, our next step will be chip fabrication. This work will include efforts to improve yield and investigate long-term reliability, which can be easily accomplished by standard techniques used to evaluate UV LEDs.

THE SiC MOSFET is guaranteed a great future. Thanks to its capability to efficiently control current at high voltages, sales are accelerating in a multitude of applications, including electric vehicles, solid-state circuit breakers, and various types of motors. Multi-billion dollar revenues are sure to follow.

However, exactly how much success the SiC MOSFET will have is not set in stone. Factors weighing heavily on this are price, performance, and reliability. And of these three, reliability is arguably the most critical. That’s because many of the adopters of this device will really value robustness, as this allows them to foster a reputation for producing products that never fail.

Efforts within the SiC community continue to take the reliability of the SiC MOSFET to a new level. At the recent International Reliability Physics Symposium (IRPS), a forum with a rich history in considering the long-term health of silicon devices, several presentations considered the robustness of the SiC MOSFET.

At this meeting, held on-line due to Covid-19 restrictions,  the likes of Infineon, STMicroelectronics and On Semiconductor provided insights into the impact of defects on the lifetime of the device, and offered options for assessing reliability of the gate oxide.

Hidden assassins

Today, most SiC devices are produced using 150 mm SiC substrates. The quality of this foundation has improved a great deal over the last two decades. However, even state-of-the-art substrates grown by physical vapour transport are far from perfect. It is the norm for them to have around ten thousand defects per square centimetre, according to conference speaker Thomas Neyer from On Semiconductor.

Neyer’s presentation considered many different forms of defect that occur in SiC MOSFETs. He explained that one common option for exposing them is to treat the material in molten potassium hydroxide, and then examine the wafer under a microscope. But he prefers to classify defects with non-destructive approaches, such as photoluminescence techniques, X-ray topography and imaging with cross-polarised light. Using these techniques to record defects allows the performance of devices to be correlated with the type of imperfection. So powerful is this approach that it is even possible to relate device performance to the actual number of defects in a particular die.

It would be easy to blame all the defects found in epiwafers on imperfections in the boule. That’s misleading, however, explained Neyer, who pointed out that they can also be introduced in the slow and costly wafering process flow, involving slicing, grinding and polishing. When substrates are formed from a boule, this creates nanoscale dislocations with open cores that hamper the quality of SiC epilayers. Neyer and his co-workers have categorised the defects found in SiC epilayers into three groups: killer visible defects, which include triangular types of defect, strong topographic defects and carrots; non-killer visible defects, such as obtuse triangles, scratches, pits and V-type defects; and non-killer crystal defects, such as stacking faults, basal plane dislocations, grain boundaries and bar stacking faults (see Figure 1 for more details).  

The answer is nuanced. For Schottky barrier diodes, an increase in non-killer defects has little impact; but for MOSFETs, the opposite is true – and when a die has more than 10 non-killer defects, this is more of concern than a killer defect. Non-killer defects are to blame for early life rejects, burn-in failures, and outliers in short circuits and avalanche tests. 

Neyer and co-workers also discovered that SiC MOSFETs with double-digit numbers of stacking faults have a wider distribution in key device characteristics. Average values for the leakage current and its standard deviation both increase markedly, while values for the breakdown voltage and threshold voltage – these depend on extraction currents – decrease as the number of stacking faults per die increases.

Encouraging results have come from benchmarking the threshold voltage stability of On Semiconductor’s MOSFETs against rival SiC products with planar and trench architectures. Using a gate-source stress at 100 kHz and a 50 percent duty cycle, this device exhibited greater stability than its three competitors used in this study (see Figure 2).     

Troublesome triangles

Studies of the role of defects on the MOSFET’s breakdown have also been conducted by a team from CNR-IMM, Italy, working in collaboration with STMicroelectronics. Speaking on behalf of this partnership, Patrick Fiorenza from CNR-IMM argued that efforts to understand infant mortality have to begin with wafer-level tests involving thousands of devices. He pointed out that it is critical to differentiate between extrinsic breakdown, which happens during the early life of a device, and intrinsic breakdown.

He added that when working at the buffer level, it is also worthwhile to check the gate current: “This is important to understand if some extrinsic failure can be intercepted before finalisation of the fabrication.” At very low electric fields – such as just 4 MV/cm, which ensures no threat of insulator damage – he and his co-workers have found that it is possible to observe gate currents that don’t follow the ideal Fowler-Nordheim behaviour. Looking at devices with this attribute in more detail, the team have identified compromised devices that failed high-temperature gate bias tests, due to surface bumps that are seen in atomic force microscopy images.

Imaging the surface of the device with a focused ion beam failed to shed any light on the cause of failure of the MOSFETs. So Fiorenza and co-workers removed the poly-silicon metal gate and the gate oxide, before inspecting the structure once more. This time they discovered triangular defects in the JFET region of the MOSFET. Using a two-beam form of transmission electron microscopy, they found a mixed edge and screw dislocation.

Speeding screening

Those needing to assess the reliability of the SiC MOSFET will welcome the introduction of a relatively straightforward, speedy technique developed by Infineon Technologies and announced at IPRS. This approach focuses on the weakness of the gate oxide, which is the key failure mechanism.

Failures due to extrinsics are a significant cause for concern, given that their prevalence is higher in SiC MOSFETs than in silicon devices. One promising option for uncovering them is to measure device performance at different voltages. “By gate-voltage screening, you mainly sort out devices with extrinsics, and reduce the field failure probability,” said Berens.

The extent of failure reduction realised by screening depends on the ratio of the screening voltage to the operating voltage – Berens refers to this as the failure reduction factor. Note that this factor exceeds a thousand when the screening voltage is three times the value of the recommended operating voltage (see Figure 4).

Of course, there are limitations on how high a voltage can be used for screening. This method of evaluation must avoid permanent damage to ‘good’ chips, accomplished by avoiding degradation caused by the tunnelling of carriers and impact ionisation. Both phenomena can lead to a negative threshold voltage shift. Berens championed a new measurement procedure that avoids using too high a stress voltage. Instead, a series of voltages are applied, each 1 V higher than the previous. After each pulse, which should be as short as possible to reduce the chances of degradation, the threshold voltage is recorded.

To illustrate the value of this approach, Berens presented an example of what one could expect when carrying out this measurement. To begin with, as the stress voltage incrementally increased, so did the threshold voltage, due to a positive bias temperature instability. But beyond a certain value the threshold voltage plummeted, reaching a point of no return and causing the device to be irreversibly damaged (see Figure 5).

Berens explained that determining the likelihood of field-rate failure requires the value for the stress voltage for the onset of irreversible degradation, along with the intended operating voltage for the MOSFET. The ratio of these two determines the failure reduction factor and gives an insight into device reliability.

Demonstrating how this works in practice, Berens compared data for a range of commercial MOSFETs, including trench and DMOS designs. Pulsed stress tests uncovered a 20 V range in voltages required to reach the onset of irreversible damage, with values depending on the thickness of the oxide. This is understandable, as thicker oxides are subjected to a weaker electric field strength that reduces the chances of impact ionisation.

For the next step in this analysis, Berens and co-workers accounted for the operating voltage of the various devices. With this factor included, the differences between manufacturers narrowed significantly; and the new, normalised ratio allowed the failure rate reduction factor to be determined by reading this value from the graph shown in Figure 4. Note that due to the high degree of non-linearity of this graph, small variations in the normalised ratio produce a difference in the failure rate reduction factor by two orders of magnitude (see Figure 6).  This implies that the most reliable devices have roughly one hundred times fewer failures in the field than the most unreliable devices.  

Berens says that one of the advantages of this method is the speed with which it determines the likelihood of failure – it takes less than a minute per test run. The technique is also straightforward, with no special test equipment required. “And last but not least, we didn’t need any special knowledge, only publicly available data sheet values.”

The problem of pits

SemiQ, a producer of SiC power devices based in California, has also been investigating the screening of SiC MOSFETs using the gate voltage. Speaking on behalf of the company, Yongju Zheng detailed measurements on 1200 V, 80 mΩ SiC planar depletion MOSFETs with a 50 nm-thick gate oxide. This investigation considered a variety of voltages and voltage ramp rates, with measurements taken at room temperature and 130 °C.

The engineers found that the failure voltage is higher when the ramp rate is faster. “This could be due to longer stress time, leading to more charging at the interface of silicon carbide and silicon dioxide,” speculated Zheng. Note that for the two temperatures used in this study, no notable difference in failure voltage is found.

Zheng and her colleagues have considered whether large epi pits could be behind the early failure of some SiC MOSFETs. “It turned out that these early failures show very strong correlation to large pit defects, that are defined as pit defects larger than 100 micron-squared.” This correlation is so strong that 80 percent of these large pits caused early failure (see Figure 7). According to Zheng, the presence of these pits may alter the epitaxial growth conditions, and lead to local oxide thinning that would result in electric field crowding – both factors could account for early failures.

“Based on the study in this work, the screening voltage is suggested to be below 38 volts for a 50 nanometre gate oxide in production,” said Zheng, adding that such a value should be low enough to detect the extrinisic failure rate, while not significantly lowering the threshold voltage of the MOSFET, or shortening the lifetime of its gate oxide.

Looking into leakage

A thorough study into the leakage current of 1.2 kV commercial SiC power MOSFETs has been conducted by researchers at Ohio State University, working in partnership with engineers at Alpha and Omega Semiconductor.

Highlighting the findings at IPRS, Shengnan Zhu from Ohio State University explained that one of the challenges with this type of study is that the device makers do not disclose the thickness of their gate oxides. So Zhu and her co-workers have had to estimate this from the value for the breakdown voltage, obtained by measuring the gate leakage current while ramping the gate voltage.

This approach indicated that the oxide in 1.2 kV power MOSFETs varies from 39 nm to 46 nm, assuming a dielectric breakdown field in the range 10 MV/cm to 11.5 MV/cm. The team also recorded variations in the gate current leakage over a 24 hour period for a range of gate voltages, while maintaining the device at an elevated temperature of 150 °C. Plotting the data revealed three regimes (see Figure 8). For gate voltages of 39 V or more, the gate current accelerates; for voltages of 38 V to 35 V, there are variations in the current, before a rapid hike; and for a voltages of 33 V or less, the current falls steadily.

Zhu offered a detailed explanation for this range of behaviour. She argued that for gate voltages of 39 V or more, corresponding to an oxide field of at least 9.8 MV/cm, hole trapping dominates. This takes place due to Fowler-Nordheim tunnelling of electrons into the device – these carriers trigger impact ionisation and generate electron-hole pairs, with holes driven to the semiconductor-oxide interface, where they are joined by additional holes resulting from anode hole injection. A high hole density at this boundary reduces the width of the barrier for tunnelling of electrons and leads to an increased injection of this carrier, which generates yet more holes through impact ionisation. With positive feedback at play, there is an acceleration of the gate leakage current. 

For voltages of 38 V to 35 V, the oxide field is slightly lower, at 9.5-9.0 MV/cm. In this case, there is also hole trapping that enhances the electric field near the interface. However, this time subsequent electron trapping in the oxide leads to a reduction in the strength of the local field, a widening of the tunnel barrier, and ultimately a reduction in leakage current. Dominance of hole trapping, followed by electron trapping, results in a rise and then a fall in the gate leakage current. When investigating this in more detail, the team found that their conjecture is supported by variations in threshold voltage.

When the gate voltage is 35 V or below, the field across the gate oxide is restricted to no more than 8.8 MV/cm. For devices operating in this regime, electron trapping takes place, relaxing the electric field. This increases the barrier width, and in turn reduces Fowler-Nordheim tunnelling. While this takes place, the threshold voltage increases.

The insights provide by Zhu and the other speakers at IPRS showcase the progress being made to understand the reliability of the SiC power MOSFET, and differences in the devices of many manufacturers.

As insights feed in to device development and production, robustness of this transistor should increase, driving its deployment in ever more applications.

THE ERA OF ‘happy scaling’, driven by Moore’s Law and played out by the semiconductor community, has faced severe challenges since 2005. Up until then progress came relatively easily, with shrinking of the silicon transistors delivering multiple benefits, including a lower power consumption, increased performance, and a reduction in the fabrication cost per transistor. A new, more powerful generation of technology launched roughly every two years – denoted by a new node size – to double the number of transistors packed into an identical-sized chip.

The first sign that the benefits of scaling would not go on forever appeared when the node-to-node performance improvements at a fixed power – referred to as Dennard scaling – started slowing down. Applying the brakes were short-channel effects. Leakage currents started shooting up, even when not applying a voltage to the gate, due to significant reductions in gate length and a shortening of the conduction channel. Scaling also caused source and drain contacts to begin to have a dramatic impact on the channel region.

To compensate for this slow-down in device improvement and allow integrated circuits to continue to advance, much effort has been directed at developing new transistor technologies. Many directions have been pursued, including new channel materials, new transistor architectures and co-optimisation of the chip’s design and its technology.

A significant architectural improvement has been the replacement of the planar MOSFET with the FinFET – the latter is now the incumbent design in mainstream chip production processes. In a FinFET, the channel takes the form of a very thin fin, positioned between source and drain terminals. Wrapping around this three-dimensional channel is a gate that provides control from three sides and combats short-channel effects. It is an architecture that has been crucial to scaling over the last decade, but will fail to provide enough electrostatic control beyond the 5 nm or 3 nm node.

Building on this approach is the vertically stacked, gate-all-around nanosheet transistor. It provides superior channel control, thanks to a gate that fully wraps around and in between the channels. At imec of Leuven, Belgium, this architecture is on our roadmap, followed by the forksheet transistor – that is a design that uses a forked gate structure to control nanosheets, and allows a far tighter n-to-p spacing than that possible with FinFET and nanosheet devices. Another candidate for well into the future is a stack of multiple channels, which could effectively extend scaling with silicon or SiGe semiconductors.

Running in parallel to this evolution, the research community has been investigating gains provided by enhancing carrier mobility. Options for the channel include strain engineering and migrating to high-mobility semiconductors, such as germanium and the III-Vs. Note that there is much interest in InGaAs: as it transports charge much faster than silicon, it promises faster speeds and lower power consumption. Innovative processes have already been developed to incorporate foreign channels with silicon CMOS, using conventional manufacturing techniques. However, just like silicon, it is unlikely that these high-mobility materials will enable sufficient gate length scaling at the very advanced nodes that lie ahead. It seems that III/V-material-based devices will find a more natural adoption in high-frequency applications – as required for (beyond-) 5G applications – that allow their high-speed properties to reach their full potential.

The promise of 2D semiconductors

To realise further gate length reduction, thinner semiconductor channels are needed to keep short channel effects under control. Migrating to thinner channels restricts the pathway for current to flow, and this limits the opportunity for charge carriers to leak when the device is turned off.

Offering much promise in this regard is a class of materials known as two-dimensional semiconductors. They include transition metal dichalcogenides, such as WS₂ and MoS₂. In these semiconductors atoms are arranged in layered crystals, with a single layer thickness of typically just 7 Å – small enough to make these materials a great choice for ensuring very thin channels. Results from theoretical studies highlight their potential, indicating that they maintain a relatively high carrier mobility, independent of channel thickness. It’s an attribute that should enable engineers to scale gate lengths below 10 nm without having to worry about short-channel effects.

The global effort at developing transition metal dichalcogenides has led to the exploration of a variety of materials, and the identification of some of the main challenges for improving device performance. To date, most work has involved semiconductor channels made of MoS₂. Devices based on this material are the most mature, with the best experimental values for mobility getting close to the theoretical value of 200 cm² V^-1 s^-1.

Recently, promising results have been reported for WS₂-based FETs. According to theoretical work, these devices have the potential to deliver an even higher performance than their MoS₂ cousins. Experimental results are also encouraging. For example, back in 2019, research reported by a TSMC-led collaboration showed that electrical characteristics, such as the

on/off ratio and the sub-threshold swing, are comparable to the best recently published values for MoS₂ n-FETs. In its turn, imec has demonstrated functional 2D-FETs with a 30 nm-long channel just 1-2 monolayers thick.

With this class of devices a dual-gated device structure improves electrostatic control. Unlike traditional FETs, which just have a gate at the top, dual-gated siblings have a top and a bottom gate – when connected, this increases electrostatic control over the channel. Measurements on our 2D-FETs with connected top and back gates reveal that they outperform single-gated counterparts in drive current (I_on), transconductance and sub-threshold swing, three key metrics for evaluating short-channel effects. Another encouraging aspect of the dual-gate structure is that it shows promise for CMOS operation. While these results suggest that a great future lies ahead for the WS₂-based FET, there is much work still to do, given that the devices we’ve just described were fabricated on relatively small coupons with patches of synthetic transition metal dichalcogenide material. To build on these hero results from lab-based devices and prepare a pathway for commercial success, an approach must be found that enables their adoption in a 300 mm integration flow.

A 300 mm platform

Several years ago, our team started working towards 300 mm integration of the family of transition metal dichalcogenide 2D semiconductors. This created a unique 300 mm test vehicle for 2D-FETs, allowing fabrication of functioning devices with gate lengths down to 18 nm. We have used the flow to study the impact of various processing conditions, such as channel deposition technology and gate stack formation. Based on these insights, we are developing improved process steps to enhance device performance.

We have found that the growth temperature impacts material quality. This conclusion came from the growth and characterisation of a layer of WS₂ deposited at 750 °C and 950 °C, using W(CO)₆ and H₂S sources. Using atomic force microscopy, we compared films grown on 300 mm silicon/SiO₂ substrates, produced using a growth time of 170 minutes, and found that a higher deposition temperature increased the size of the WS₂ grains. The higher temperature also improved crystallinity and reduced the defectivity of the WS₂ layer, according to photoluminescence and Raman measurements. It is possible that larger crystal sizes could be obtained at lower temperatures using different precursors or other deposition techniques – this is a topic of further research.

One of the challenges associated with producing WS₂ is that it is not easy to deposit insulating materials on top of the 2D surface and form a gate dielectric. An intrinsically passivated process is to blame. When traditional ALD processes are adopted, relying on nucleation of surface dangling bonds, growth only occurs at defect sites. Since the MOCVD-grown WS₂ has relatively few defect sites, this hinders direct oxide deposition.

Results on our devices formed on 300 mm wafers reveal that their performance is an order of magnitude lower than it is for reported lab devices. For example, on-current is typically just 10 μA/mm. To understand why these devices are inferior, we have considered the integrated flow. Our characterisation of dual-gated devices with source/drain side contacts suggests that channel material crystallinity is the biggest challenge to improving device performance. Success requires further breakthroughs in material growth and processing. We also have room for improvement in the processes used to form gates, dope material and add contacts.

While MOCVD is the preferred technique for depositing high-quality 2D semiconductor channels, the high temperatures that are used threaten to exceed the thermal budget. Options to prevent this from happening include introducing different precursors and switching to alternative deposition technologies. There is also the more radical, complex approach of using a transfer process to move the 2D channel to a pre-patterned 300 mm silicon wafer.

Evaluating variability

Efforts at imec have not been limited to just developing and integrating 2D-based transistors. We have also undertaken the first-ever variability study of a large set of nanoscale lab-based 2D-FET devices, using transistors with a channel width of 115 nm and lengths of 100 nm and below. This investigation considered various sources of variability – including the thickness of the 2D-channel; the presence of bilayer islands, such as grains; and the 2D growth template – and the respective impact on electrical performance, with a focus on the sub-threshold regime.

Within this study, there have been simulations, along with the construction of devices that have a median sub-threshold slope of 80 mV/dec and maximum on-current in excess of 100 μA/mm. This research uncovered a strongly reduced sub-threshold slope and threshold-voltage variability when thinning the 2D material from three monolayers to one. This is an encouraging result, indicating that very thin channels are needed for further transistor scaling. For atom-thick channels, this work shows that the intrinsic variability is low, and comparable with silicon FinFETs. To make further progress in driving down device variability, so that it is suitable for future nodes, there needs to be better control of key process steps, like cleaning and contacts.

Worldwide progress with 2D-FETs is positioning this class of transistor as a prime candidate for extending the logic device scaling roadmap. At imec, work by our team and our colleagues has started to lay the groundwork for introducing 2D semiconductors into a 300 mm integration flow – a key requirement for industrial adoption. We have already taken significant steps by improving device performance and developing a fundamental understanding of this form of FET.

This work is the result of a collaborative effort of a broad imec team working on exploratory logic.

WHILE MANY OF YOU KNOW quite a bit about LEDs, lasers and solar cells, it’s possible that you have never heard of the wavelength blocker. Yet despite its low profile it is produced in high volumes, playing a key role in today’s optical networks, as it serves as the smallest unit of a wavelength-selective switch.

The deployment of wavelengths blockers is on an upward trajectory, driven by technologies such as 5G, Cloud computing and the Internet of Things. In all these applications, it is essential to efficiently utilize the available bandwidth within the optical fibre network.

In order to understand the role of the wavelength blocker, you must first get to grips with the basics of dense wavelength division multiplexing (DWDM), a technology based on bringing together optical signals at different wavelengths and transmitting all this aggregated information through an optical fibre.

A key component in these networks is the optical add/drop multiplexer (OADM). It taps (that is, drops) information at some wavelengths, while sending it on at other wavelengths. Another attribute of the OADM is that it can add new wavelengths onto an optical fibre, allowing additional signals to be transported to other destinations.

The first generation of OADMs connected spectral demultiplexers and multiplexers by a fibre patch cord. The downside of this arrangement is that it did not have any capability to be reconfigured – that required manual intervention to change the wavelength dropped or added. This weakness stemmed from employing a fixed wavelength for port mapping in the spectral multiplexing/demultiplexing devices, and resulted in the need to physically disconnect fibre patch cords during reconfiguration. Such a state of affairs is clearly undesirable. It is far better to avoid any manual intervention – and that motivated the migration to a new form of OADM that has dynamic reconfigurability.

It is this more sophisticated successor that lies at the backbone of today’s high-capacity optical network, enabling dynamic transport of traffic in a manner that leads to efficient use of bandwidth and network resources. Note that the WSS enables independent switching of any wavelength to any port, without restrictions imposed by the switching of other wavelengths.

Marrying materials

Lying at the heart of a WSS are a number wavelength blockers (WBLs), each with one input port and one output port. Several research groups have demonstrated WBLs using silicon photonics, but they are compromised by a poor on/off switching ratio and a high insertion loss, attributed to a large port count. As this platform does not have the capability to include a gain section that compensates for on-chip power losses, it is not an ideal candidate for implementing a WBL.

Another material for making a WBL is InP. Its strength is that it can compensate for on-chip losses by incorporating semiconductor optical amplifiers (SOAs), which also provide a high on/off switching ratio. But the limited wafer size of InP hampers scaling to a large wavelength and port count.

Our team at Eindhoven University of Technology, The Netherlands, working in partnership with engineers at VTT Research Institute, Finland, has broken new ground by fabricating the first ever hybrid WBL. Collaborating through an EU project named PASSION – its full name is Photonic technologies for progrAmmable transmission and switching modular systems based on Scalable Spectrum/space aggregation for future agIle high capacity metrO Networks – we are taking on the ambitious goal of developing a software-defined network featuring transceiver and switching node technology for high capacity metropolitan optical networks. The goal is to reach a capacity as high as 8 Tbit/s per second per polarization, using 160 wavelength channels within the C-band, with transmission routed down a single fibre.

Demonstrating devices

We have demonstrated the proof-of-concept of our hybrid WBL by designing and fabricating a pair of chips on silicon photonic and InP platforms (see Figure 2 for the mask layouts of two 1 x 12 arrayed waveguide gratings formed using silicon photonics and an array of 12 SOA gates on InP). By placing SOA switching gates in a U-shape, we allow input/output straight waveguides to be accessed from the same side. Flip-chip bonding unites the silicon photonics and InP chips, and realizes the hybrid WBL. As well as housing de-multiplexer and multiplexer arrayed waveguide gratings, the silicon photonics chip has a cavity, designed to accommodate the InP chip during flip-chip bonding assembly.

In our hybrid chip, waveguides are formed in InP and silicon (see Figure 3). Those formed in silicon, based on VTT’s 3 μm by 3 μm waveguide technology, provide a polarization-insensitive performance that doubles the transmission capacity per wavelength channel – data can be simultaneously transmitted in transverse electric and the transverse magnetic polarizations. The InP waveguide features a 0.5 μm-thick InGaAsP core. Due to the difference in the size of this core and that in silicon, to ensure that hybrid coupling losses are below 3 dB when the waveguides are brought together, their air-gap must be less than 2 μm, and the alignment accuracy must be below ± 0.5 μm in the vertical and lateral directions.

Flip-chip bonding provides us with a placement accuracy below 0.5 μm in the vertical and lateral directions. However, a limitation of the visual system that we use for bonding is that it prevents us from precisely controlling the airgap between the two chip facets, resulting in an air gap of the order 8 μm; this leads to excess coupling losses between silicon photonics and InP waveguides.

Channel characteristics

We have characterized our hybrid WBL electrically and optically. Of the ten wavelength channels, eight are working – they are channels Ch1, Ch3, …, Ch9. The most likely reason that two channels are not working is optical damage at the waveguide facets of the SOAs, occurring during the flip-chip bonding process.

After optimally tuning the current for each gate SOA to minimize fibre-to-fibre loss and the effect of back reflection on the hybrid WBL, fibre-to-fibre losses for Ch1, Ch3, Ch6, Ch7, Ch8 range from 32.2 dB to 37.5 dB. Such high losses stem from the large air gap, which needs to be below 2 μm in the horizontal direction to keep hybrid coupling losses below 3 dB. To help address this loss, we plan to move to on-chip integrated spot-size converters, because they relax the tight airgap tolerance. Another improvement that we will be making is to introduce angled waveguides – they alleviate the impact of back reflection and fully employ the gain of SOAs.

To evaluate data transmission, we have employed a tuneable laser source to generate the wavelengths corresponding to the channels of the WBL, and used 10 Gbit/s NRZ 2⁷-1 and 20 Gbit/s NRZ 2³¹-1 PRBS patterns (see Figure 8). Using 10 Gbit/s signals,  measurements of the bit error rate at various received powers produced clearly opened eye diagrams for Ch1, Ch3, Ch6, Ch7, and Ch8 (see Figure 9). Power penalties range from 0.3 dB to 1.5 dB.When data transmission capacity increased to 20 Gbit/s, we still observed clear eye diagrams and obtained error-free performance (see Figure 10). Power penalties ranged from 0.7 dB in the case of Ch3 to 2.8 dB in the case of Ch8 (see Table 2 for the power penalty at a bit error rate of 1 x 10^-9).

The road ahead

Success to date has enabled us to demonstrate a proof-of-concept hybrid WBL module that is based on silicon photonic passives and InP actives. For this we used a flip-chip bonding process to produce just four samples, undoubtedly a small number for such an assembly process. We are now laying the foundations for trimming hybrid coupling loss between the silicon photonic and InP waveguides, and maximizing the yield of the flip-chip bonding assembly process.

For both of these applications, our WBL benefits from the large degree of integration associated with silicon photonics. We can scale the number of wavelength channels per WBL up to 40 and enjoy a wide operating range, thanks to the optical transparency of the silicon photonics VTT waveguide technology through O and L bands. Another strength of our technology is that the SOA switching gates span a substantial spectra range, and can be optimised for O, E, S, C and L bands. This provides multi-band WSS functionality, a major asset in high-capacity metro and data centre networks.

Our WSS could also have a role to play in data centre networks, which provide full connectivity to thousands of servers hosting various applications, such as cloud computing, big data and IoT. In these networks, optical switches can help to support high bandwidth, and are a promising candidate to replace the electronic switches that struggle in this regard. A move to optical switches can also trim power consumption in these networks by eliminating electrical-optical-electrical conversion, which is essential when using electrical switches.

Figure 10.  The bit error rate (BER) as a function of received power and eye diagram at 20 Gbit/s.

While there is still much to do to improve and refine our hybrid chip, by uniting the best attributes of silicon photonics with the strengths of InP, this device clearly has much to offer.

Figure 11. In this network, the L1 node is a high-capacity ROADM node, equipped with colour-less, direction-less, contention-less capability. This node can transparently switch space-division multiplexed systems via Fan-out and Fan-in of multi-core fibre bundles. The photonic space switch handles traffic flow in the spatial domain in the express in/out path. Incoming express-in traffic is either sent forward directly as by-pass traffic, or directed to the disaggregate switch in the drop path as drop traffic. Operating in a similar manner, this switch adds traffic in the express-out path. The WSS (drop) acts as a disaggregating switch, while the WSS (add) provides an aggregating switch. Working together, they offer dynamic reconfigurability. When traffic has a common destination it is bundled and sent forward in the express-out path so that, at the next L1 node, express ports transparently direct the traffic. The L1 node also enables adding/dropping of traffic from/to the access Level-2 (L2) network, which has L2 nodes with 2-degree ROADMs based on a WBL and 1:2 splitter and 2:1 combiner. In addition, there are local add/drop functionalities at the L1 node. They are embedded at the WSS: in the add directions via sliceable bandwidth variable transmitters (SBVTs); and in the drop direction via multi-cast switches (MCS) and coherent receiver modules (CRM).